From 0ef1cb29f70c71d3c85f5b8b4ad3c7ce60babba8 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 23 Oct 2023 01:09:36 +0200 Subject: stm32/rcc: merge wb into l4/l5. --- examples/stm32wl/src/bin/lora_lorawan.rs | 1 + examples/stm32wl/src/bin/lora_p2p_receive.rs | 19 ++++++++++++++++++- examples/stm32wl/src/bin/lora_p2p_send.rs | 19 ++++++++++++++++++- examples/stm32wl/src/bin/random.rs | 1 + examples/stm32wl/src/bin/rtc.rs | 26 ++++++++++++++++++++------ 5 files changed, 58 insertions(+), 8 deletions(-) (limited to 'examples') diff --git a/examples/stm32wl/src/bin/lora_lorawan.rs b/examples/stm32wl/src/bin/lora_lorawan.rs index e26c274ad..35a6a8425 100644 --- a/examples/stm32wl/src/bin/lora_lorawan.rs +++ b/examples/stm32wl/src/bin/lora_lorawan.rs @@ -39,6 +39,7 @@ async fn main(_spawner: Spawner) { config.rcc.hse = Some(Hse { freq: Hertz(32_000_000), mode: HseMode::Bypass, + prescaler: HsePrescaler::DIV1, }); config.rcc.mux = ClockSrc::PLL1_R; config.rcc.pll = Some(Pll { diff --git a/examples/stm32wl/src/bin/lora_p2p_receive.rs b/examples/stm32wl/src/bin/lora_p2p_receive.rs index be33f39c1..1c485d739 100644 --- a/examples/stm32wl/src/bin/lora_p2p_receive.rs +++ b/examples/stm32wl/src/bin/lora_p2p_receive.rs @@ -11,6 +11,7 @@ use embassy_lora::iv::{InterruptHandler, Stm32wlInterfaceVariant}; use embassy_stm32::bind_interrupts; use embassy_stm32::gpio::{Level, Output, Pin, Speed}; use embassy_stm32::spi::Spi; +use embassy_stm32::time::Hertz; use embassy_time::{Delay, Timer}; use lora_phy::mod_params::*; use lora_phy::sx1261_2::SX1261_2; @@ -26,7 +27,23 @@ bind_interrupts!(struct Irqs{ #[embassy_executor::main] async fn main(_spawner: Spawner) { let mut config = embassy_stm32::Config::default(); - config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE; + { + use embassy_stm32::rcc::*; + config.rcc.hse = Some(Hse { + freq: Hertz(32_000_000), + mode: HseMode::Bypass, + prescaler: HsePrescaler::DIV1, + }); + config.rcc.mux = ClockSrc::PLL1_R; + config.rcc.pll = Some(Pll { + source: PLLSource::HSE, + prediv: PllPreDiv::DIV2, + mul: PllMul::MUL6, + divp: None, + divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG + divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2) + }); + } let p = embassy_stm32::init(config); let spi = Spi::new_subghz(p.SUBGHZSPI, p.DMA1_CH1, p.DMA1_CH2); diff --git a/examples/stm32wl/src/bin/lora_p2p_send.rs b/examples/stm32wl/src/bin/lora_p2p_send.rs index 85f6a84b7..3afa78acb 100644 --- a/examples/stm32wl/src/bin/lora_p2p_send.rs +++ b/examples/stm32wl/src/bin/lora_p2p_send.rs @@ -11,6 +11,7 @@ use embassy_lora::iv::{InterruptHandler, Stm32wlInterfaceVariant}; use embassy_stm32::bind_interrupts; use embassy_stm32::gpio::{Level, Output, Pin, Speed}; use embassy_stm32::spi::Spi; +use embassy_stm32::time::Hertz; use embassy_time::Delay; use lora_phy::mod_params::*; use lora_phy::sx1261_2::SX1261_2; @@ -26,7 +27,23 @@ bind_interrupts!(struct Irqs{ #[embassy_executor::main] async fn main(_spawner: Spawner) { let mut config = embassy_stm32::Config::default(); - config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE; + { + use embassy_stm32::rcc::*; + config.rcc.hse = Some(Hse { + freq: Hertz(32_000_000), + mode: HseMode::Bypass, + prescaler: HsePrescaler::DIV1, + }); + config.rcc.mux = ClockSrc::PLL1_R; + config.rcc.pll = Some(Pll { + source: PLLSource::HSE, + prediv: PllPreDiv::DIV2, + mul: PllMul::MUL6, + divp: None, + divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG + divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2) + }); + } let p = embassy_stm32::init(config); let spi = Spi::new_subghz(p.SUBGHZSPI, p.DMA1_CH1, p.DMA1_CH2); diff --git a/examples/stm32wl/src/bin/random.rs b/examples/stm32wl/src/bin/random.rs index 2cf7ef9d0..1a8822b42 100644 --- a/examples/stm32wl/src/bin/random.rs +++ b/examples/stm32wl/src/bin/random.rs @@ -21,6 +21,7 @@ async fn main(_spawner: Spawner) { config.rcc.hse = Some(Hse { freq: Hertz(32_000_000), mode: HseMode::Bypass, + prescaler: HsePrescaler::DIV1, }); config.rcc.mux = ClockSrc::PLL1_R; config.rcc.pll = Some(Pll { diff --git a/examples/stm32wl/src/bin/rtc.rs b/examples/stm32wl/src/bin/rtc.rs index 9ebb05f22..b3b7f9c5c 100644 --- a/examples/stm32wl/src/bin/rtc.rs +++ b/examples/stm32wl/src/bin/rtc.rs @@ -5,20 +5,34 @@ use chrono::{NaiveDate, NaiveDateTime}; use defmt::*; use embassy_executor::Spawner; -use embassy_stm32::rcc::{ClockSrc, LsConfig}; use embassy_stm32::rtc::{Rtc, RtcConfig}; +use embassy_stm32::time::Hertz; use embassy_stm32::Config; use embassy_time::Timer; use {defmt_rtt as _, panic_probe as _}; #[embassy_executor::main] async fn main(_spawner: Spawner) { - let p = { - let mut config = Config::default(); - config.rcc.mux = ClockSrc::HSE; + let mut config = Config::default(); + { + use embassy_stm32::rcc::*; config.rcc.ls = LsConfig::default_lse(); - embassy_stm32::init(config) - }; + config.rcc.hse = Some(Hse { + freq: Hertz(32_000_000), + mode: HseMode::Bypass, + prescaler: HsePrescaler::DIV1, + }); + config.rcc.mux = ClockSrc::PLL1_R; + config.rcc.pll = Some(Pll { + source: PLLSource::HSE, + prediv: PllPreDiv::DIV2, + mul: PllMul::MUL6, + divp: None, + divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG + divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2) + }); + } + let p = embassy_stm32::init(config); info!("Hello World!"); let now = NaiveDate::from_ymd_opt(2020, 5, 15) -- cgit From a39ae12edcf23935df82d547fb2d997ca6b7c8d5 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 23 Oct 2023 01:48:09 +0200 Subject: stm32/rcc: misc cleanups. --- examples/stm32h5/src/bin/eth.rs | 4 ++-- examples/stm32h5/src/bin/usb_serial.rs | 4 ++-- examples/stm32h7/src/bin/adc.rs | 7 ++++--- examples/stm32h7/src/bin/camera.rs | 6 +++--- examples/stm32h7/src/bin/dac.rs | 7 ++++--- examples/stm32h7/src/bin/dac_dma.rs | 7 ++++--- examples/stm32h7/src/bin/eth.rs | 6 +++--- examples/stm32h7/src/bin/eth_client.rs | 6 +++--- examples/stm32h7/src/bin/fmc.rs | 6 +++--- examples/stm32h7/src/bin/low_level_timer_api.rs | 6 +++--- examples/stm32h7/src/bin/pwm.rs | 6 +++--- examples/stm32h7/src/bin/sdmmc.rs | 6 +++--- examples/stm32h7/src/bin/spi.rs | 6 +++--- examples/stm32h7/src/bin/spi_dma.rs | 6 +++--- examples/stm32h7/src/bin/usb_serial.rs | 6 +++--- 15 files changed, 46 insertions(+), 43 deletions(-) (limited to 'examples') diff --git a/examples/stm32h5/src/bin/eth.rs b/examples/stm32h5/src/bin/eth.rs index 6e40f0ac0..5bec9d447 100644 --- a/examples/stm32h5/src/bin/eth.rs +++ b/examples/stm32h5/src/bin/eth.rs @@ -43,7 +43,7 @@ async fn main(spawner: Spawner) -> ! { mode: HseMode::BypassDigital, }); config.rcc.pll1 = Some(Pll { - source: PllSource::Hse, + source: PllSource::HSE, prediv: PllPreDiv::DIV2, mul: PllMul::MUL125, divp: Some(PllDiv::DIV2), @@ -54,7 +54,7 @@ async fn main(spawner: Spawner) -> ! { config.rcc.apb1_pre = APBPrescaler::DIV1; config.rcc.apb2_pre = APBPrescaler::DIV1; config.rcc.apb3_pre = APBPrescaler::DIV1; - config.rcc.sys = Sysclk::Pll1P; + config.rcc.sys = Sysclk::PLL1_P; config.rcc.voltage_scale = VoltageScale::Scale0; let p = embassy_stm32::init(config); info!("Hello World!"); diff --git a/examples/stm32h5/src/bin/usb_serial.rs b/examples/stm32h5/src/bin/usb_serial.rs index 3b3c38e17..735826a69 100644 --- a/examples/stm32h5/src/bin/usb_serial.rs +++ b/examples/stm32h5/src/bin/usb_serial.rs @@ -30,7 +30,7 @@ async fn main(_spawner: Spawner) { mode: HseMode::BypassDigital, }); config.rcc.pll1 = Some(Pll { - source: PllSource::Hse, + source: PllSource::HSE, prediv: PllPreDiv::DIV2, mul: PllMul::MUL125, divp: Some(PllDiv::DIV2), // 250mhz @@ -41,7 +41,7 @@ async fn main(_spawner: Spawner) { config.rcc.apb1_pre = APBPrescaler::DIV4; config.rcc.apb2_pre = APBPrescaler::DIV2; config.rcc.apb3_pre = APBPrescaler::DIV4; - config.rcc.sys = Sysclk::Pll1P; + config.rcc.sys = Sysclk::PLL1_P; config.rcc.voltage_scale = VoltageScale::Scale0; let p = embassy_stm32::init(config); diff --git a/examples/stm32h7/src/bin/adc.rs b/examples/stm32h7/src/bin/adc.rs index 4a358a35f..e367827e9 100644 --- a/examples/stm32h7/src/bin/adc.rs +++ b/examples/stm32h7/src/bin/adc.rs @@ -14,10 +14,10 @@ async fn main(_spawner: Spawner) { let mut config = Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), @@ -25,13 +25,14 @@ async fn main(_spawner: Spawner) { divr: None, }); config.rcc.pll2 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV8), // 100mhz divq: None, divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz diff --git a/examples/stm32h7/src/bin/camera.rs b/examples/stm32h7/src/bin/camera.rs index 8195430b2..23ece1c38 100644 --- a/examples/stm32h7/src/bin/camera.rs +++ b/examples/stm32h7/src/bin/camera.rs @@ -28,17 +28,17 @@ async fn main(_spawner: Spawner) { let mut config = Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), divq: Some(PllDiv::DIV8), // 100mhz divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz diff --git a/examples/stm32h7/src/bin/dac.rs b/examples/stm32h7/src/bin/dac.rs index 821221897..35fd6550f 100644 --- a/examples/stm32h7/src/bin/dac.rs +++ b/examples/stm32h7/src/bin/dac.rs @@ -16,10 +16,10 @@ fn main() -> ! { let mut config = Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), @@ -27,13 +27,14 @@ fn main() -> ! { divr: None, }); config.rcc.pll2 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV8), // 100mhz divq: None, divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz diff --git a/examples/stm32h7/src/bin/dac_dma.rs b/examples/stm32h7/src/bin/dac_dma.rs index 334986a05..e141fc484 100644 --- a/examples/stm32h7/src/bin/dac_dma.rs +++ b/examples/stm32h7/src/bin/dac_dma.rs @@ -24,10 +24,10 @@ async fn main(spawner: Spawner) { let mut config = embassy_stm32::Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), @@ -35,13 +35,14 @@ async fn main(spawner: Spawner) { divr: None, }); config.rcc.pll2 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV8), // 100mhz divq: None, divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz diff --git a/examples/stm32h7/src/bin/eth.rs b/examples/stm32h7/src/bin/eth.rs index 81d9c7347..e37d8797b 100644 --- a/examples/stm32h7/src/bin/eth.rs +++ b/examples/stm32h7/src/bin/eth.rs @@ -34,18 +34,18 @@ async fn main(spawner: Spawner) -> ! { let mut config = Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; config.rcc.hsi48 = true; // needed for RNG - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), divq: None, divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz diff --git a/examples/stm32h7/src/bin/eth_client.rs b/examples/stm32h7/src/bin/eth_client.rs index 338137069..88df53f01 100644 --- a/examples/stm32h7/src/bin/eth_client.rs +++ b/examples/stm32h7/src/bin/eth_client.rs @@ -35,18 +35,18 @@ async fn main(spawner: Spawner) -> ! { let mut config = Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; config.rcc.hsi48 = true; // needed for RNG - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), divq: None, divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz diff --git a/examples/stm32h7/src/bin/fmc.rs b/examples/stm32h7/src/bin/fmc.rs index cffd47093..54e2c3629 100644 --- a/examples/stm32h7/src/bin/fmc.rs +++ b/examples/stm32h7/src/bin/fmc.rs @@ -14,17 +14,17 @@ async fn main(_spawner: Spawner) { let mut config = Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), divq: Some(PllDiv::DIV8), // 100mhz divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz diff --git a/examples/stm32h7/src/bin/low_level_timer_api.rs b/examples/stm32h7/src/bin/low_level_timer_api.rs index 0355ac073..e4bac8a5a 100644 --- a/examples/stm32h7/src/bin/low_level_timer_api.rs +++ b/examples/stm32h7/src/bin/low_level_timer_api.rs @@ -17,18 +17,18 @@ async fn main(_spawner: Spawner) { let mut config = Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; config.rcc.hsi48 = true; // needed for RNG - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), divq: Some(PllDiv::DIV8), // 100mhz divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz diff --git a/examples/stm32h7/src/bin/pwm.rs b/examples/stm32h7/src/bin/pwm.rs index 973a10cdd..c55d780a0 100644 --- a/examples/stm32h7/src/bin/pwm.rs +++ b/examples/stm32h7/src/bin/pwm.rs @@ -17,17 +17,17 @@ async fn main(_spawner: Spawner) { let mut config = Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), divq: None, divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz diff --git a/examples/stm32h7/src/bin/sdmmc.rs b/examples/stm32h7/src/bin/sdmmc.rs index ecb8d6542..be968ff77 100644 --- a/examples/stm32h7/src/bin/sdmmc.rs +++ b/examples/stm32h7/src/bin/sdmmc.rs @@ -18,17 +18,17 @@ async fn main(_spawner: Spawner) -> ! { let mut config = Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), divq: Some(PllDiv::DIV4), // default clock chosen by SDMMCSEL. 200 Mhz divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz diff --git a/examples/stm32h7/src/bin/spi.rs b/examples/stm32h7/src/bin/spi.rs index f128d4a56..a8db0ff77 100644 --- a/examples/stm32h7/src/bin/spi.rs +++ b/examples/stm32h7/src/bin/spi.rs @@ -40,17 +40,17 @@ fn main() -> ! { let mut config = Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz. divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz diff --git a/examples/stm32h7/src/bin/spi_dma.rs b/examples/stm32h7/src/bin/spi_dma.rs index d4c0bcdbd..561052e48 100644 --- a/examples/stm32h7/src/bin/spi_dma.rs +++ b/examples/stm32h7/src/bin/spi_dma.rs @@ -36,17 +36,17 @@ fn main() -> ! { let mut config = Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz. divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz diff --git a/examples/stm32h7/src/bin/usb_serial.rs b/examples/stm32h7/src/bin/usb_serial.rs index c1e5144be..19d77183b 100644 --- a/examples/stm32h7/src/bin/usb_serial.rs +++ b/examples/stm32h7/src/bin/usb_serial.rs @@ -23,18 +23,18 @@ async fn main(_spawner: Spawner) { let mut config = Config::default(); { use embassy_stm32::rcc::*; - config.rcc.hsi = Some(Hsi::Mhz64); + config.rcc.hsi = Some(HSIPrescaler::DIV1); config.rcc.csi = true; config.rcc.hsi48 = true; // needed for USB - config.rcc.pll_src = PllSource::Hsi; config.rcc.pll1 = Some(Pll { + source: PllSource::HSI, prediv: PllPreDiv::DIV4, mul: PllMul::MUL50, divp: Some(PllDiv::DIV2), divq: None, divr: None, }); - config.rcc.sys = Sysclk::Pll1P; // 400 Mhz + config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz -- cgit