From b58cc2aa239e4adba2c32462cc89133bb7d9f698 Mon Sep 17 00:00:00 2001
From: kbleeke <pluth@0t.re>
Date: Thu, 2 Mar 2023 19:02:32 +0100
Subject: use irqs to wait for events

---
 src/bus.rs | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

(limited to 'src/bus.rs')

diff --git a/src/bus.rs b/src/bus.rs
index 7700a832a..6ec5d0bd6 100644
--- a/src/bus.rs
+++ b/src/bus.rs
@@ -19,6 +19,9 @@ pub trait SpiBusCyw43 {
     /// Backplane reads have a response delay that produces one extra unspecified word at the beginning of `read`.
     /// Callers that want to read `n` word from the backplane, have to provide a slice that is `n+1` words long.
     async fn cmd_read(&mut self, write: u32, read: &mut [u32]);
+
+    async fn wait_for_event(&mut self);
+    fn clear_event(&mut self);
 }
 
 pub(crate) struct Bus<PWR, SPI> {
@@ -63,7 +66,8 @@ where
         trace!("{:#010b}", (val & 0xff));
 
         // 32-bit word length, little endian (which is the default endianess).
-        self.write32_swapped(REG_BUS_CTRL, WORD_LENGTH_32 | HIGH_SPEED).await;
+        self.write32_swapped(REG_BUS_CTRL, WORD_LENGTH_32 | HIGH_SPEED | INTERRUPT_HIGH | WAKE_UP)
+            .await;
 
         let val = self.read8(FUNC_BUS, REG_BUS_CTRL).await;
         trace!("{:#b}", val);
@@ -297,6 +301,14 @@ where
 
         self.spi.cmd_write(&buf).await;
     }
+
+    pub async fn wait_for_event(&mut self) {
+        self.spi.wait_for_event().await;
+    }
+
+    pub fn clear_event(&mut self) {
+        self.spi.clear_event();
+    }
 }
 
 fn swap16(x: u32) -> u32 {
-- 
cgit 


From 8926397f4592f22a5ed54f772a979578ca36628f Mon Sep 17 00:00:00 2001
From: kbleeke <pluth@0t.re>
Date: Mon, 27 Mar 2023 14:37:39 +0200
Subject: address irq nits

---
 src/bus.rs | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'src/bus.rs')

diff --git a/src/bus.rs b/src/bus.rs
index 6ec5d0bd6..d2a249f97 100644
--- a/src/bus.rs
+++ b/src/bus.rs
@@ -1,5 +1,6 @@
 use core::slice;
 
+use embassy_futures::yield_now;
 use embassy_time::{Duration, Timer};
 use embedded_hal_1::digital::OutputPin;
 use futures::FutureExt;
@@ -20,8 +21,11 @@ pub trait SpiBusCyw43 {
     /// Callers that want to read `n` word from the backplane, have to provide a slice that is `n+1` words long.
     async fn cmd_read(&mut self, write: u32, read: &mut [u32]);
 
-    async fn wait_for_event(&mut self);
-    fn clear_event(&mut self);
+    /// Wait for events from the Device. A typical implementation would wait for the IRQ pin to be high.
+    /// The default implementation always reports ready, resulting in active polling of the device.
+    async fn wait_for_event(&mut self) {
+        yield_now().await;
+    }
 }
 
 pub(crate) struct Bus<PWR, SPI> {
@@ -305,10 +309,6 @@ where
     pub async fn wait_for_event(&mut self) {
         self.spi.wait_for_event().await;
     }
-
-    pub fn clear_event(&mut self) {
-        self.spi.clear_event();
-    }
 }
 
 fn swap16(x: u32) -> u32 {
-- 
cgit