From a8ca36cdbe06e83019279e441ac386a448c12edb Mon Sep 17 00:00:00 2001
From: James Munns <james@onevariable.com>
Date: Mon, 17 Nov 2025 14:58:26 +0100
Subject: Fill in main_clk state

---
 src/clocks/mod.rs | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'src/clocks/mod.rs')

diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs
index c6606b1b6..40acb11ec 100644
--- a/src/clocks/mod.rs
+++ b/src/clocks/mod.rs
@@ -87,7 +87,12 @@ pub fn init(settings: ClocksConfig) -> Result<(), ClockError> {
     operator.configure_firc_clocks()?;
     operator.configure_sirc_clocks()?;
     operator.configure_fro16k_clocks()?;
-    // TODO, everything downstream
+
+    // For now, just use FIRC as the main/cpu clock, which should already be
+    // the case on reset
+    assert!(operator.scg0.rccr().read().scs().is_firc());
+    assert_eq!(operator.syscon.ahbclkdiv().read().div().bits(), 0);
+    operator.clocks.main_clk = Some(operator.clocks.fro_hf_root.clone().unwrap());
 
     critical_section::with(|cs| {
         let mut clks = CLOCKS.borrow_ref_mut(cs);
-- 
cgit