From 77b2c602a60e41c7c977003a6d40367ac285930e Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 13 Nov 2025 13:17:44 -0800 Subject: Move examples to a package of their own (#16) * Move examples to a package of their own * cargo +nightly fmt * Add missing safety doc * cargo clippy examples * fmt again --------- Co-authored-by: Felipe Balbi --- src/lib.rs | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) (limited to 'src/lib.rs') diff --git a/src/lib.rs b/src/lib.rs index 9899564d8..4e5ac0109 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -62,29 +62,29 @@ pub fn init(cfg: crate::config::Config) -> Peripherals { peripherals } -/// Optional hook called by cortex-m-rt before RAM init. -/// We proactively mask and clear all NVIC IRQs to avoid wedges from stale state -/// left by soft resets/debug sessions. -/// -/// NOTE: Manual VTOR setup is required for RAM execution. The cortex-m-rt 'set-vtor' -/// feature is incompatible with our setup because it expects __vector_table to be -/// defined differently than how our RAM-based linker script arranges it. -#[no_mangle] -pub unsafe extern "C" fn __pre_init() { - // Set the VTOR to point to the interrupt vector table in RAM - // This is required since code runs from RAM on this MCU - crate::interrupt::vtor_set_ram_vector_base(0x2000_0000 as *const u32); +// /// Optional hook called by cortex-m-rt before RAM init. +// /// We proactively mask and clear all NVIC IRQs to avoid wedges from stale state +// /// left by soft resets/debug sessions. +// /// +// /// NOTE: Manual VTOR setup is required for RAM execution. The cortex-m-rt 'set-vtor' +// /// feature is incompatible with our setup because it expects __vector_table to be +// /// defined differently than how our RAM-based linker script arranges it. +// #[no_mangle] +// pub unsafe extern "C" fn __pre_init() { +// // Set the VTOR to point to the interrupt vector table in RAM +// // This is required since code runs from RAM on this MCU +// crate::interrupt::vtor_set_ram_vector_base(0x2000_0000 as *const u32); - // Mask and clear pending for all NVIC lines (0..127) to avoid stale state across runs. - let nvic = &*cortex_m::peripheral::NVIC::PTR; - for i in 0..4 { - // 4 words x 32 = 128 IRQs - nvic.icer[i].write(0xFFFF_FFFF); - nvic.icpr[i].write(0xFFFF_FFFF); - } - // Do NOT touch peripheral registers here: clocks may be off and accesses can fault. - crate::interrupt::clear_default_handler_snapshot(); -} +// // Mask and clear pending for all NVIC lines (0..127) to avoid stale state across runs. +// let nvic = &*cortex_m::peripheral::NVIC::PTR; +// for i in 0..4 { +// // 4 words x 32 = 128 IRQs +// nvic.icer[i].write(0xFFFF_FFFF); +// nvic.icpr[i].write(0xFFFF_FFFF); +// } +// // Do NOT touch peripheral registers here: clocks may be off and accesses can fault. +// crate::interrupt::clear_default_handler_snapshot(); +// } /// Internal helper to dispatch a type-level interrupt handler. #[inline(always)] -- cgit