From e75066820ad320495ca70570641c90d75247b19b Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Fri, 7 Nov 2025 10:07:33 -0800 Subject: cargo +nightly fmt Signed-off-by: Felipe Balbi --- src/adc.rs | 24 ++++++------------ src/clocks.rs | 3 +-- src/gpio.rs | 8 +++--- src/interrupt.rs | 6 ++--- src/lib.rs | 12 ++++----- src/lpuart/buffered.rs | 19 +++------------ src/lpuart/mod.rs | 19 +++++---------- src/ostimer.rs | 66 +++++++++++++++++--------------------------------- src/pins.rs | 5 +--- src/rtc.rs | 3 ++- src/uart.rs | 13 +++++----- 11 files changed, 61 insertions(+), 117 deletions(-) (limited to 'src') diff --git a/src/adc.rs b/src/adc.rs index 5625330e9..d456971f7 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,7 +1,7 @@ //! ADC driver -use crate::pac; use core::sync::atomic::{AtomicBool, Ordering}; +use crate::pac; use crate::pac::adc1::cfg::{HptExdi, Pwrsel, Refsel, Tcmdres, Tprictrl, Tres}; use crate::pac::adc1::cmdh1::{Avgs, Cmpen, Next, Sts}; use crate::pac::adc1::cmdl1::{Adch, Ctype, Mode}; @@ -140,14 +140,10 @@ impl Adc { .variant(match config.trigger_priority_policy { TriggerPriorityPolicy::ConvPreemptSoftlyNotAutoResumed | TriggerPriorityPolicy::ConvPreemptSoftlyAutoRestarted - | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed => { - Tprictrl::FinishCurrentOnPriority - } + | TriggerPriorityPolicy::ConvPreemptSoftlyAutoResumed => Tprictrl::FinishCurrentOnPriority, TriggerPriorityPolicy::ConvPreemptSubsequentlyNotAutoResumed | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoRestarted - | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => { - Tprictrl::FinishSequenceOnPriority - } + | TriggerPriorityPolicy::ConvPreemptSubsequentlyAutoResumed => Tprictrl::FinishSequenceOnPriority, _ => Tprictrl::AbortCurrentOnPriority, }) .tres() @@ -176,12 +172,8 @@ impl Adc { }); if config.enable_conv_pause { - adc.pause().modify(|_, w| unsafe { - w.pauseen() - .enabled() - .pausedly() - .bits(config.conv_pause_delay) - }); + adc.pause() + .modify(|_, w| unsafe { w.pauseen().enabled().pausedly().bits(config.conv_pause_delay) }); } else { adc.pause().write(|w| unsafe { w.bits(0) }); } @@ -247,8 +239,7 @@ impl Adc { pub fn do_auto_calibration(&self) { let adc = unsafe { &*I::ptr() }; - adc.ctrl() - .modify(|_, w| w.cal_req().calibration_request_pending()); + adc.ctrl().modify(|_, w| w.cal_req().calibration_request_pending()); while adc.gcc0().read().rdy().is_gain_cal_not_valid() {} @@ -260,8 +251,7 @@ impl Adc { let gcra = 131072.0 / (131072.0 - gcca as f32); // Write to GCR0 - adc.gcr0() - .write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) }); + adc.gcr0().write(|w| unsafe { w.bits(self.get_gain_conv_result(gcra)) }); adc.gcr0().modify(|_, w| w.rdy().set_bit()); diff --git a/src/clocks.rs b/src/clocks.rs index 95d7ad567..65a17cef6 100644 --- a/src/clocks.rs +++ b/src/clocks.rs @@ -76,8 +76,7 @@ pub unsafe fn enable_ostimer0(peripherals: &pac::Peripherals) { pub unsafe fn select_uart2_clock(peripherals: &pac::Peripherals) { // Use FRO_LF_DIV (already running) MUX=0 DIV=0 let mrcc = &peripherals.mrcc0; - mrcc.mrcc_lpuart2_clksel() - .write(|w| w.mux().clkroot_func_0()); + mrcc.mrcc_lpuart2_clksel().write(|w| w.mux().clkroot_func_0()); mrcc.mrcc_lpuart2_clkdiv().write(|w| unsafe { w.bits(0) }); } diff --git a/src/gpio.rs b/src/gpio.rs index faeefd333..1e7214b28 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -66,7 +66,7 @@ pub trait PinId { } pub mod pins { - use super::{AnyPin, PinId, pac}; + use super::{pac, AnyPin, PinId}; macro_rules! define_pin { ($Name:ident, $port:literal, $pin:literal, $GpioBlk:ident) => { @@ -130,15 +130,13 @@ impl<'d> Flex<'d> { pub fn set_as_input(&mut self) { let mask = self.mask(); let gpio = self.gpio(); - gpio.pddr() - .modify(|r, w| unsafe { w.bits(r.bits() & !mask) }); + gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() & !mask) }); } pub fn set_as_output(&mut self) { let mask = self.mask(); let gpio = self.gpio(); - gpio.pddr() - .modify(|r, w| unsafe { w.bits(r.bits() | mask) }); + gpio.pddr().modify(|r, w| unsafe { w.bits(r.bits() | mask) }); } pub fn set_high(&mut self) { diff --git a/src/interrupt.rs b/src/interrupt.rs index d91e6479a..09d7acbef 100644 --- a/src/interrupt.rs +++ b/src/interrupt.rs @@ -6,11 +6,11 @@ mod generated { embassy_hal_internal::interrupt_mod!(OS_EVENT, LPUART2, RTC, ADC1); } -pub use generated::interrupt::Priority; -pub use generated::interrupt::typelevel; +use core::sync::atomic::{AtomicU16, AtomicU32, Ordering}; + +pub use generated::interrupt::{typelevel, Priority}; use crate::pac::Interrupt; -use core::sync::atomic::{AtomicU16, AtomicU32, Ordering}; /// Trait for configuring and controlling interrupts. /// diff --git a/src/lib.rs b/src/lib.rs index 518fe01d2..fe27aadba 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -30,17 +30,17 @@ pub fn pac() -> &'static pac::Peripherals { } } -#[cfg(feature = "unstable-pac")] -pub use mcxa_pac as pac; -#[cfg(not(feature = "unstable-pac"))] -pub(crate) use mcxa_pac as pac; - // Use cortex-m-rt's #[interrupt] attribute directly; PAC does not re-export it. // Re-export interrupt traits and types pub use adc::Adc1 as Adc1Token; -pub use gpio::{AnyPin, Flex, Gpio as GpioToken, Input, Level, Output, pins::*}; +pub use gpio::pins::*; +pub use gpio::{AnyPin, Flex, Gpio as GpioToken, Input, Level, Output}; pub use interrupt::InterruptExt; +#[cfg(feature = "unstable-pac")] +pub use mcxa_pac as pac; +#[cfg(not(feature = "unstable-pac"))] +pub(crate) use mcxa_pac as pac; pub use ostimer::Ostimer0 as Ostimer0Token; pub use rtc::Rtc0 as Rtc0Token; pub use uart::Lpuart2 as Uart2Token; diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs index e2382e86d..0413fed8e 100644 --- a/src/lpuart/buffered.rs +++ b/src/lpuart/buffered.rs @@ -3,8 +3,8 @@ use core::marker::PhantomData; use core::sync::atomic::{AtomicBool, Ordering}; use core::task::Poll; -use embassy_hal_internal::Peri; use embassy_hal_internal::atomic_ring_buffer::RingBuffer; +use embassy_hal_internal::Peri; use embassy_sync::waitqueue::AtomicWaker; use super::*; @@ -87,15 +87,7 @@ impl<'a> BufferedLpuart<'a> { let state = T::buffered_state(); // Initialize the peripheral - Self::init::( - Some(&tx_pin), - Some(&rx_pin), - None, - None, - tx_buffer, - rx_buffer, - config, - )?; + Self::init::(Some(&tx_pin), Some(&rx_pin), None, None, tx_buffer, rx_buffer, config)?; Ok(Self { tx: BufferedLpuartTx { @@ -523,9 +515,7 @@ pub struct BufferedInterruptHandler { _phantom: PhantomData, } -impl crate::interrupt::typelevel::Handler - for BufferedInterruptHandler -{ +impl crate::interrupt::typelevel::Handler for BufferedInterruptHandler { unsafe fn on_interrupt() { let regs = T::info().regs; let state = T::buffered_state(); @@ -616,8 +606,7 @@ impl crate::interrupt::typelevel::Handler // If buffer is empty, switch to TC interrupt or disable if state.tx_buf.is_empty() { cortex_m::interrupt::free(|_| { - regs.ctrl() - .modify(|_, w| w.tie().disabled().tcie().enabled()); + regs.ctrl().modify(|_, w| w.tie().disabled().tcie().enabled()); }); } } diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs index 99f4a4a66..bed10bdb0 100644 --- a/src/lpuart/mod.rs +++ b/src/lpuart/mod.rs @@ -1,15 +1,13 @@ -use crate::interrupt; use core::marker::PhantomData; + use embassy_hal_internal::{Peri, PeripheralType}; use paste::paste; -use crate::pac; use crate::pac::lpuart0::baud::Sbns as StopBits; -use crate::pac::lpuart0::ctrl::{ - Idlecfg as IdleConfig, Ilt as IdleType, M as DataBits, Pt as Parity, -}; +use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits}; use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource}; use crate::pac::lpuart0::stat::Msbf as MsbFirst; +use crate::{interrupt, pac}; pub mod buffered; @@ -261,8 +259,7 @@ pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock: Clock) -> Result /// Configure frame format (stop bits, data bits) pub fn configure_frame_format(regs: Regs, config: &Config) { // Configure stop bits - regs.baud() - .modify(|_, w| w.sbns().variant(config.stop_bits_count)); + regs.baud().modify(|_, w| w.sbns().variant(config.stop_bits_count)); // Clear M10 for now (10-bit mode) regs.baud().modify(|_, w| w.m10().disabled()); @@ -314,8 +311,7 @@ pub fn configure_fifo(regs: Regs, config: &Config) { }); // Enable TX/RX FIFOs - regs.fifo() - .modify(|_, w| w.txfe().enabled().rxfe().enabled()); + regs.fifo().modify(|_, w| w.txfe().enabled().rxfe().enabled()); // Flush FIFOs regs.fifo() @@ -818,10 +814,7 @@ impl<'a> LpuartTx<'a, Blocking> { } fn write_byte_internal(&mut self, byte: u8) -> Result<()> { - self.info - .regs - .data() - .modify(|_, w| unsafe { w.bits(u32::from(byte)) }); + self.info.regs.data().modify(|_, w| unsafe { w.bits(u32::from(byte)) }); Ok(()) } diff --git a/src/ostimer.rs b/src/ostimer.rs index 6a4188db0..a4cab6970 100644 --- a/src/ostimer.rs +++ b/src/ostimer.rs @@ -27,9 +27,10 @@ //! - Immediate wake for timestamps that would cause rollover issues #![allow(dead_code)] +use core::sync::atomic::{AtomicBool, Ordering}; + use crate::interrupt::InterruptExt; use crate::pac; -use core::sync::atomic::{AtomicBool, Ordering}; // PAC defines the shared RegisterBlock under `ostimer0`. type Regs = pac::ostimer0::RegisterBlock; @@ -129,18 +130,12 @@ pub(super) fn wait_for_match_write_complete(r: &Regs) -> bool { fn prime_match_registers(r: &Regs) { // Disable the interrupt, clear any pending flag, then wait until the MATCH registers are writable. - r.osevent_ctrl().write(|w| { - w.ostimer_intrflag() - .clear_bit_by_one() - .ostimer_intena() - .clear_bit() - }); + r.osevent_ctrl() + .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); if wait_for_match_write_ready(r) { - r.match_l() - .write(|w| unsafe { w.match_value().bits(MATCH_L_MAX) }); - r.match_h() - .write(|w| unsafe { w.match_value().bits(MATCH_H_MAX) }); + r.match_l().write(|w| unsafe { w.match_value().bits(MATCH_L_MAX) }); + r.match_h().write(|w| unsafe { w.match_value().bits(MATCH_H_MAX) }); let _ = wait_for_match_write_complete(r); } } @@ -222,10 +217,7 @@ impl<'d, I: Instance> Ostimer<'d, I> { /// Requires clocks for the instance to be enabled by the board before calling. /// Does not enable NVIC or INTENA; use time_driver::init() for async operation. pub fn new(_inst: impl Instance, cfg: Config, _p: &'d crate::pac::Peripherals) -> Self { - assert!( - cfg.clock_frequency_hz > 0, - "OSTIMER frequency must be greater than 0" - ); + assert!(cfg.clock_frequency_hz > 0, "OSTIMER frequency must be greater than 0"); if cfg.init_match_max { let r: &Regs = unsafe { &*I::ptr() }; @@ -268,12 +260,8 @@ impl<'d, I: Instance> Ostimer<'d, I> { // Mask the peripheral interrupt flag before we toggle the reset line so that // no new NVIC activity races with the reset sequence. - r.osevent_ctrl().write(|w| { - w.ostimer_intrflag() - .clear_bit_by_one() - .ostimer_intena() - .clear_bit() - }); + r.osevent_ctrl() + .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); unsafe { crate::reset::assert::(peripherals); @@ -287,9 +275,7 @@ impl<'d, I: Instance> Ostimer<'d, I> { crate::reset::release::(peripherals); } - while !::is_released( - &peripherals.mrcc0, - ) { + while !::is_released(&peripherals.mrcc0) { cortex_m::asm::nop(); } @@ -363,12 +349,8 @@ impl<'d, I: Instance> Ostimer<'d, I> { critical_section::with(|_| { // Disable interrupt and clear flag - r.osevent_ctrl().write(|w| { - w.ostimer_intrflag() - .clear_bit_by_one() - .ostimer_intena() - .clear_bit() - }); + r.osevent_ctrl() + .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); if !wait_for_match_write_ready(r) { prime_match_registers(r); @@ -526,15 +508,17 @@ fn gray_to_bin(gray: u64) -> u64 { } pub mod time_driver { - use super::{ - ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, ALARM_TARGET_TIME, EVTIMER_HI_MASK, - EVTIMER_HI_SHIFT, LOW_32_BIT_MASK, Regs, bin_to_gray, now_ticks_read, - }; - use crate::pac; use core::sync::atomic::Ordering; use core::task::Waker; + use embassy_sync::waitqueue::AtomicWaker; use embassy_time_driver as etd; + + use super::{ + bin_to_gray, now_ticks_read, Regs, ALARM_ACTIVE, ALARM_CALLBACK, ALARM_FLAG, ALARM_TARGET_TIME, + EVTIMER_HI_MASK, EVTIMER_HI_SHIFT, LOW_32_BIT_MASK, + }; + use crate::pac; pub struct Driver; static TIMER_WAKER: AtomicWaker = AtomicWaker::new(); @@ -569,12 +553,8 @@ pub mod time_driver { critical_section::with(|_| { // Mask INTENA and clear flag - r.osevent_ctrl().write(|w| { - w.ostimer_intrflag() - .clear_bit_by_one() - .ostimer_intena() - .clear_bit() - }); + r.osevent_ctrl() + .write(|w| w.ostimer_intrflag().clear_bit_by_one().ostimer_intena().clear_bit()); // Read back to ensure W1C took effect on hardware let _ = r.osevent_ctrl().read().ostimer_intrflag().bit(); @@ -690,9 +670,7 @@ pub mod time_driver { /// Type-level handler to be used with bind_interrupts! for OS_EVENT. pub struct OsEventHandler; - impl crate::interrupt::typelevel::Handler - for OsEventHandler - { + impl crate::interrupt::typelevel::Handler for OsEventHandler { unsafe fn on_interrupt() { on_interrupt(); } diff --git a/src/pins.rs b/src/pins.rs index 1d92f9fef..f802568f3 100644 --- a/src/pins.rs +++ b/src/pins.rs @@ -84,10 +84,7 @@ pub unsafe fn set_pin_mux(port: u8, pin: u8, mux: u8) { }; if pin > max_pin { - panic!( - "Invalid pin {} for PORT{}, max pin is {}", - pin, port, max_pin - ); + panic!("Invalid pin {} for PORT{}, max pin is {}", pin, port, max_pin); } // Get the base address for the port diff --git a/src/rtc.rs b/src/rtc.rs index 5e3dfe6c1..d62da1f0a 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -1,7 +1,8 @@ //! RTC DateTime driver. +use core::sync::atomic::{AtomicBool, Ordering}; + use crate::pac; use crate::pac::rtc0::cr::Um; -use core::sync::atomic::{AtomicBool, Ordering}; type Regs = pac::rtc0::RegisterBlock; diff --git a/src/uart.rs b/src/uart.rs index 65dd91492..3209a318d 100644 --- a/src/uart.rs +++ b/src/uart.rs @@ -1,11 +1,13 @@ //! Minimal polling UART2 bring-up replicating MCUXpresso hello_world ordering. //! WARNING: This is a narrow implementation only for debug console (115200 8N1). -use crate::pac; use core::cell::RefCell; + use cortex_m::interrupt::Mutex; use embassy_sync::signal::Signal; +use crate::pac; + // svd2rust defines the shared LPUART RegisterBlock under lpuart0; all instances reuse it. type Regs = pac::lpuart0::RegisterBlock; @@ -108,7 +110,7 @@ impl Uart { cortex_m::asm::delay(3); // Short delay for reset to take effect l.global().write(|w| w.rst().no_effect()); cortex_m::asm::delay(10); // Allow peripheral to stabilize after reset - // 2) BAUD + // 2) BAUD let (osr, sbr) = compute_osr_sbr(cfg.src_hz, cfg.baud); l.baud().modify(|_, w| { let w = match cfg.stop_bits { @@ -234,8 +236,7 @@ impl RingBuffer { // Global RX buffer shared between interrupt handler and UART instance static RX_BUFFER: Mutex> = Mutex::new(RefCell::new(RingBuffer::new())); -static RX_SIGNAL: Signal = - Signal::new(); +static RX_SIGNAL: Signal = Signal::new(); // Debug counter for interrupt handler calls static mut INTERRUPT_COUNT: u32 = 0; @@ -279,9 +280,7 @@ impl Uart { /// Type-level handler for LPUART2 interrupts, compatible with bind_interrupts!. pub struct UartInterruptHandler; -impl crate::interrupt::typelevel::Handler - for UartInterruptHandler -{ +impl crate::interrupt::typelevel::Handler for UartInterruptHandler { unsafe fn on_interrupt() { INTERRUPT_COUNT += 1; -- cgit