From b6fc19182b4ae02ea1e9107ca28b88f4a3b0b60a Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Thu, 23 Sep 2021 14:43:17 +0200 Subject: Add pwr for L1 and update RCC to new reg block --- stm32-data | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'stm32-data') diff --git a/stm32-data b/stm32-data index 7f5f8e7c6..18df82005 160000 --- a/stm32-data +++ b/stm32-data @@ -1 +1 @@ -Subproject commit 7f5f8e7c641d74a0e97e2d84bac61b7c6c267a7e +Subproject commit 18df82005f29da14e7d4c442f7cff3a46939c434 -- cgit