From cd2f28d2abb5b66981b7fdbb32566e6b942c7a54 Mon Sep 17 00:00:00 2001 From: Lachezar Lechev Date: Fri, 24 Mar 2023 12:14:38 +0200 Subject: chore: add spi_async tests for uneven buffers Signed-off-by: Lachezar Lechev --- tests/rp/src/bin/spi_async.rs | 44 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/rp/src/bin/spi_async.rs b/tests/rp/src/bin/spi_async.rs index 6c85ef60a..e3fe6e84c 100644 --- a/tests/rp/src/bin/spi_async.rs +++ b/tests/rp/src/bin/spi_async.rs @@ -1,3 +1,6 @@ +//! Make sure to connect GPIO pins 3 (`PIN_3`) and 4 (`PIN_4`) together +//! to run this test. +//! #![no_std] #![no_main] #![feature(type_alias_impl_trait)] @@ -18,10 +21,43 @@ async fn main(_spawner: Spawner) { let mut spi = Spi::new(p.SPI0, clk, mosi, miso, p.DMA_CH0, p.DMA_CH1, Config::default()); - let tx_buf = [1_u8, 2, 3, 4, 5, 6]; - let mut rx_buf = [0_u8; 6]; - spi.transfer(&mut rx_buf, &tx_buf).await.unwrap(); - assert_eq!(rx_buf, tx_buf); + // equal rx & tx buffers + { + let tx_buf = [1_u8, 2, 3, 4, 5, 6]; + let mut rx_buf = [0_u8; 6]; + spi.transfer(&mut rx_buf, &tx_buf).await.unwrap(); + assert_eq!(rx_buf, tx_buf); + } + + // tx > rx buffer + { + let tx_buf = [7_u8, 8, 9, 10, 11, 12]; + + let mut rx_buf = [0_u8, 3]; + spi.transfer(&mut rx_buf, &tx_buf).await.unwrap(); + assert_eq!(rx_buf, tx_buf[..3]); + } + + // we make sure to that clearing FIFO works after the uneven buffers + + // equal rx & tx buffers + { + let tx_buf = [13_u8, 14, 15, 16, 17, 18]; + let mut rx_buf = [0_u8; 6]; + spi.transfer(&mut rx_buf, &tx_buf).await.unwrap(); + + assert_eq!(rx_buf, tx_buf); + } + + // rx > tx buffer + { + let tx_buf = [19_u8, 20, 21]; + let mut rx_buf = [0_u8; 6]; + spi.transfer(&mut rx_buf, &tx_buf).await.unwrap(); + + assert_eq!(rx_buf[..3], tx_buf, "only the first 3 TX bytes should have been received in the RX buffer"); + assert_eq!(rx_buf[3..], [0, 0, 0], "the rest of the RX bytes should be empty"); + } info!("Test OK"); cortex_m::asm::bkpt(); -- cgit From 7be63b3468f72fc684267c90093a00e77cff1bdc Mon Sep 17 00:00:00 2001 From: Lachezar Lechev Date: Sun, 26 Mar 2023 18:14:17 +0300 Subject: fix: spi transfer bug and additions to test Signed-off-by: Lachezar Lechev --- tests/rp/src/bin/spi_async.rs | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/rp/src/bin/spi_async.rs b/tests/rp/src/bin/spi_async.rs index e3fe6e84c..2e22c9de7 100644 --- a/tests/rp/src/bin/spi_async.rs +++ b/tests/rp/src/bin/spi_async.rs @@ -33,9 +33,11 @@ async fn main(_spawner: Spawner) { { let tx_buf = [7_u8, 8, 9, 10, 11, 12]; - let mut rx_buf = [0_u8, 3]; + let mut rx_buf = [0_u8; 3]; spi.transfer(&mut rx_buf, &tx_buf).await.unwrap(); assert_eq!(rx_buf, tx_buf[..3]); + + defmt::info!("tx > rx buffer - OK"); } // we make sure to that clearing FIFO works after the uneven buffers @@ -45,18 +47,36 @@ async fn main(_spawner: Spawner) { let tx_buf = [13_u8, 14, 15, 16, 17, 18]; let mut rx_buf = [0_u8; 6]; spi.transfer(&mut rx_buf, &tx_buf).await.unwrap(); - assert_eq!(rx_buf, tx_buf); + + defmt::info!("buffer rx length == tx length - OK"); } // rx > tx buffer { let tx_buf = [19_u8, 20, 21]; let mut rx_buf = [0_u8; 6]; + + // we should have written dummy data to tx buffer to sync clock. spi.transfer(&mut rx_buf, &tx_buf).await.unwrap(); - assert_eq!(rx_buf[..3], tx_buf, "only the first 3 TX bytes should have been received in the RX buffer"); + assert_eq!( + rx_buf[..3], + tx_buf, + "only the first 3 TX bytes should have been received in the RX buffer" + ); assert_eq!(rx_buf[3..], [0, 0, 0], "the rest of the RX bytes should be empty"); + defmt::info!("buffer rx length > tx length - OK"); + } + + // equal rx & tx buffers + { + let tx_buf = [22_u8, 23, 24, 25, 26, 27]; + let mut rx_buf = [0_u8; 6]; + spi.transfer(&mut rx_buf, &tx_buf).await.unwrap(); + + assert_eq!(rx_buf, tx_buf); + defmt::info!("buffer rx length = tx length - OK"); } info!("Test OK"); -- cgit