From 8911a4d8558cd41244af2be2bce2b0969a4ffbea Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Sun, 5 Nov 2023 03:06:13 +0100 Subject: stm32/rcc: switch to modern api for l0, l1. --- tests/stm32/src/common.rs | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) (limited to 'tests') diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs index ff808281a..54e23e436 100644 --- a/tests/stm32/src/common.rs +++ b/tests/stm32/src/common.rs @@ -460,23 +460,25 @@ pub fn config() -> Config { #[cfg(feature = "stm32l073rz")] { use embassy_stm32::rcc::*; - config.rcc.mux = ClockSrc::PLL( - // 32Mhz clock (16 * 4 / 2) - PLLSource::HSI, - PLLMul::MUL4, - PLLDiv::DIV2, - ); + config.rcc.hsi = true; + config.rcc.pll = Some(Pll { + source: PLLSource::HSI, + mul: PLLMul::MUL4, + div: PLLDiv::DIV2, // 32Mhz clock (16 * 4 / 2) + }); + config.rcc.mux = ClockSrc::PLL1_P; } #[cfg(any(feature = "stm32l152re"))] { use embassy_stm32::rcc::*; - config.rcc.mux = ClockSrc::PLL( - // 32Mhz clock (16 * 4 / 2) - PLLSource::HSI, - PLLMul::MUL4, - PLLDiv::DIV2, - ); + config.rcc.hsi = true; + config.rcc.pll = Some(Pll { + source: PLLSource::HSI, + mul: PLLMul::MUL4, + div: PLLDiv::DIV2, // 32Mhz clock (16 * 4 / 2) + }); + config.rcc.mux = ClockSrc::PLL1_P; } config -- cgit