From ae266f3bf528c334c4712cd37305d2bcb71c0936 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 4 Mar 2024 00:03:07 +0100
Subject: stm32/rcc: port c0 to new api. Add c0 HSIKER/HSISYS support.

---
 tests/stm32/src/common.rs | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'tests')

diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 1587a6fb4..3297ea7e2 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -260,6 +260,17 @@ pub fn config() -> Config {
     #[allow(unused_mut)]
     let mut config = Config::default();
 
+    #[cfg(feature = "stm32c031c6")]
+    {
+        config.rcc.hsi = Some(Hsi {
+            sys_div: HsiSysDiv::DIV1, // 48Mhz
+            ker_div: HsiKerDiv::DIV3, // 16Mhz
+        });
+        config.rcc.sys = Sysclk::HSISYS;
+        config.rcc.ahb_pre = AHBPrescaler::DIV1;
+        config.rcc.apb1_pre = APBPrescaler::DIV1;
+    }
+
     #[cfg(feature = "stm32g071rb")]
     {
         config.rcc.hsi = true;
-- 
cgit