From fb67fe0a6c155191534955f1230dccaea0e11a94 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Wed, 1 May 2024 02:21:06 +0200 Subject: stm32: add support for STM32H7[RS] "bootflash line", add HIL tests. --- tests/stm32/.cargo/config.toml | 2 +- tests/stm32/Cargo.toml | 1 + tests/stm32/src/bin/cordic.rs | 7 ++++++- tests/stm32/src/bin/fdcan.rs | 14 ++++++++++++++ tests/stm32/src/bin/gpio.rs | 7 ++++++- tests/stm32/src/bin/hash.rs | 3 ++- tests/stm32/src/common.rs | 33 ++++++++++++++++++++++++++++++++- 7 files changed, 62 insertions(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/stm32/.cargo/config.toml b/tests/stm32/.cargo/config.toml index 528bd3451..8752da59b 100644 --- a/tests/stm32/.cargo/config.toml +++ b/tests/stm32/.cargo/config.toml @@ -4,7 +4,7 @@ [target.'cfg(all(target_arch = "arm", target_os = "none"))'] runner = "teleprobe client run" -#runner = "teleprobe local run --chip STM32F103C8 --elf" +#runner = "teleprobe local run --chip STM32H7S3L8Hx --elf" rustflags = [ # Code-size optimizations. diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml index 30669b88c..6afa2a68e 100644 --- a/tests/stm32/Cargo.toml +++ b/tests/stm32/Cargo.toml @@ -32,6 +32,7 @@ stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng", "hash"] stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"] stm32f091rc = ["embassy-stm32/stm32f091rc", "cm0", "not-gpdma", "chrono"] stm32h503rb = ["embassy-stm32/stm32h503rb", "rng", "stop"] +stm32h7s3l8 = ["embassy-stm32/stm32h7s3l8", "rng", "cordic", "hash"] # TODO: fdcan crashes, cryp dma hangs. cryp = [] hash = [] diff --git a/tests/stm32/src/bin/cordic.rs b/tests/stm32/src/bin/cordic.rs index 400e10207..e09226de8 100644 --- a/tests/stm32/src/bin/cordic.rs +++ b/tests/stm32/src/bin/cordic.rs @@ -67,7 +67,12 @@ async fn main(_spawner: Spawner) { #[cfg(feature = "stm32g491re")] let (mut write_dma, mut read_dma) = (dp.DMA1_CH4, dp.DMA1_CH5); - #[cfg(any(feature = "stm32h563zi", feature = "stm32u585ai", feature = "stm32u5a5zj"))] + #[cfg(any( + feature = "stm32h563zi", + feature = "stm32u585ai", + feature = "stm32u5a5zj", + feature = "stm32h7s3l8" + ))] let (mut write_dma, mut read_dma) = (dp.GPDMA1_CH0, dp.GPDMA1_CH1); // calculate first result using blocking mode diff --git a/tests/stm32/src/bin/fdcan.rs b/tests/stm32/src/bin/fdcan.rs index b0c0cd82e..20bd3f7e3 100644 --- a/tests/stm32/src/bin/fdcan.rs +++ b/tests/stm32/src/bin/fdcan.rs @@ -74,6 +74,20 @@ fn options() -> (Config, TestOptions) { ) } +#[cfg(any(feature = "stm32h7s3l8"))] +fn options() -> (Config, TestOptions) { + use embassy_stm32::rcc; + let mut c = config(); + c.rcc.mux.fdcansel = rcc::mux::Fdcansel::HSE; + ( + c, + TestOptions { + max_latency: Duration::from_micros(1200), + max_buffered: 3, + }, + ) +} + #[cfg(any(feature = "stm32g491re", feature = "stm32g431cb"))] fn options() -> (Config, TestOptions) { info!("G4 config"); diff --git a/tests/stm32/src/bin/gpio.rs b/tests/stm32/src/bin/gpio.rs index c4e2fe161..dfa299ab5 100644 --- a/tests/stm32/src/bin/gpio.rs +++ b/tests/stm32/src/bin/gpio.rs @@ -216,7 +216,12 @@ async fn main(_spawner: Spawner) { } fn delay() { - #[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi", feature = "stm32h7a3zi"))] + #[cfg(any( + feature = "stm32h755zi", + feature = "stm32h753zi", + feature = "stm32h7a3zi", + feature = "stm32h7s3l8" + ))] cortex_m::asm::delay(9000); cortex_m::asm::delay(1000); } diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs index 8cc5d593f..5f54ea435 100644 --- a/tests/stm32/src/bin/hash.rs +++ b/tests/stm32/src/bin/hash.rs @@ -26,7 +26,8 @@ bind_interrupts!(struct Irqs { feature = "stm32h563zi", feature = "stm32h503rb", feature = "stm32u5a5zj", - feature = "stm32u585ai" + feature = "stm32u585ai", + feature = "stm32h7s3l8" ))] bind_interrupts!(struct Irqs { HASH => hash::InterruptHandler; diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs index 24d33dc3b..07c61956f 100644 --- a/tests/stm32/src/common.rs +++ b/tests/stm32/src/common.rs @@ -60,6 +60,8 @@ teleprobe_meta::target!(b"nucleo-stm32wba52cg"); teleprobe_meta::target!(b"nucleo-stm32f091rc"); #[cfg(feature = "stm32h503rb")] teleprobe_meta::target!(b"nucleo-stm32h503rb"); +#[cfg(feature = "stm32h7s3l8")] +teleprobe_meta::target!(b"nucleo-stm32h7s3l8"); macro_rules! define_peris { ($($name:ident = $peri:ident,)* $(@irq $irq_name:ident = $irq_code:tt,)*) => { @@ -249,6 +251,13 @@ define_peris!( SPI = SPI1, SPI_SCK = PB4, SPI_MOSI = PA15, SPI_MISO = PB3, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1, @irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler;}, ); +#[cfg(feature = "stm32h7s3l8")] +define_peris!( + CRYP_IN_DMA = GPDMA1_CH0, CRYP_OUT_DMA = GPDMA1_CH1, + UART = USART1, UART_TX = PB14, UART_RX = PA10, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1, + SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PB5, SPI_MISO = PA6, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1, + @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler;}, +); pub fn config() -> Config { #[allow(unused_mut)] @@ -641,6 +650,28 @@ pub fn config() -> Config { }); config.rcc.sys = Sysclk::PLL1_R; } - + #[cfg(any(feature = "stm32h7s3l8"))] + { + config.rcc.hse = Some(Hse { + freq: Hertz(24_000_000), + mode: HseMode::Oscillator, + }); + config.rcc.pll1 = Some(Pll { + source: PllSource::HSE, + prediv: PllPreDiv::DIV3, + mul: PllMul::MUL150, + divp: Some(PllDiv::DIV2), // 600Mhz + divq: Some(PllDiv::DIV25), // 48Mhz + divr: None, + }); + config.rcc.sys = Sysclk::PLL1_P; // 600 Mhz + config.rcc.ahb_pre = AHBPrescaler::DIV2; // 300 Mhz + config.rcc.apb1_pre = APBPrescaler::DIV2; // 150 Mhz + config.rcc.apb2_pre = APBPrescaler::DIV2; // 150 Mhz + config.rcc.apb4_pre = APBPrescaler::DIV2; // 150 Mhz + config.rcc.apb5_pre = APBPrescaler::DIV2; // 150 Mhz + config.rcc.voltage_scale = VoltageScale::HIGH; + config.rcc.mux.spi1sel = mux::Spi123sel::PLL1_Q; + } config } -- cgit