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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2021-10-26 11:59:14 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-10-26 11:59:14 +0000 |
| commit | 01e5376b2531ccd97ee760ef1dd7c3ec5d82ccfb (patch) | |
| tree | 452b6c0b0d1a6d940651e4d5ca4c1be925a14687 /.github/workflows | |
| parent | f8bd9d2b1c801236a11261c5fc0a7239ded644e4 (diff) | |
| parent | e55726964d8852a2b1fa0c3d677588f5abf518b0 (diff) | |
Merge #456
456: Fix L4 clock setup for MSI and PLL to allow RNG operation r=Dirbaio a=lulf
Example is tested on STM32L475VG.
Co-authored-by: Ulf Lilleengen <[email protected]>
Diffstat (limited to '.github/workflows')
0 files changed, 0 insertions, 0 deletions