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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2022-06-19 21:34:08 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2022-06-19 21:34:08 +0000 |
| commit | e4fbfaf5682aea8b20ffd559bfbbbbc0edf957a4 (patch) | |
| tree | cd0c92cfe7c5b8c61bd530fedd943aa4df5dcea7 /.github | |
| parent | 6852e05c59bece57b10659531665187f073b40be (diff) | |
| parent | 31e80067387f7ac85221d004deaad9d1bf3460e6 (diff) | |
Merge #804
804: Preliminary RISCV support r=Dirbaio a=MabezDev
- ~~Moves the default Interrupt implementation into a cortex_m specific module~~
- Adds a RISCV32 executor based on [osobiehl](https://github.com/osobiehl)'s work in [esp32c3 mess work](https://github.com/osobiehl/riscv-embassy-mess-work)
(FYI esp implementation of embassy traits etc, is being developed [here](https://github.com/esp-rs/esp-hal/tree/feature/embassy))
[bonus ascii cinema](https://asciinema.org/a/500857 )
Co-authored-by: Scott Mabin <[email protected]>
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