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authorchemicstry <[email protected]>2022-03-17 18:23:47 +0200
committerchemicstry <[email protected]>2022-03-17 18:23:47 +0200
commit051c6350ea5340d860dde0cea1b4c21e4f4884b6 (patch)
tree4c28da953137e1abd87bb66c5bb6e7a734886fb8
parent75e5b397996fee4934295b628dc326502354efc4 (diff)
Make UART futures Send
-rw-r--r--embassy-stm32/src/usart/mod.rs9
1 files changed, 4 insertions, 5 deletions
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 80d928786..83cdd66b9 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -106,8 +106,8 @@ impl<'d, T: Instance, TxDma> UartTx<'d, T, TxDma> {
106 reg.set_dmat(true); 106 reg.set_dmat(true);
107 }); 107 });
108 } 108 }
109 let dst = tdr(T::regs()); 109 let transfer = crate::dma::write(ch, request, buffer, tdr(T::regs()));
110 crate::dma::write(ch, request, buffer, dst).await; 110 transfer.await;
111 Ok(()) 111 Ok(())
112 } 112 }
113 113
@@ -150,9 +150,8 @@ impl<'d, T: Instance, RxDma> UartRx<'d, T, RxDma> {
150 reg.set_dmar(true); 150 reg.set_dmar(true);
151 }); 151 });
152 } 152 }
153 let r = T::regs(); 153 let transfer = crate::dma::read(ch, request, rdr(T::regs()), buffer);
154 let src = rdr(r); 154 transfer.await;
155 crate::dma::read(ch, request, src, buffer).await;
156 Ok(()) 155 Ok(())
157 } 156 }
158 157