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authoreverdrone <[email protected]>2025-11-11 15:21:37 +0100
committereverdrone <[email protected]>2025-11-11 15:21:37 +0100
commit0528e3daa386dc2ee7bb9e4a4ee3e1c979e6c479 (patch)
tree268ce8e6c2f4d9b94b3568ae859ab72a4c27dfa6
parent647c6f5f6969ab291130a50384cd2f26b167e008 (diff)
enable peripherals low power mode
-rw-r--r--embassy-stm32/src/rcc/n6.rs185
1 files changed, 185 insertions, 0 deletions
diff --git a/embassy-stm32/src/rcc/n6.rs b/embassy-stm32/src/rcc/n6.rs
index 5d2003325..5e66e1e86 100644
--- a/embassy-stm32/src/rcc/n6.rs
+++ b/embassy-stm32/src/rcc/n6.rs
@@ -329,6 +329,14 @@ fn init_clocks(config: Config, input: &ClocksInput) -> ClocksOutput {
329 let ppre4 = periph_prescaler_to_value(config.apb4.to_bits()); 329 let ppre4 = periph_prescaler_to_value(config.apb4.to_bits());
330 let ppre5 = periph_prescaler_to_value(config.apb5.to_bits()); 330 let ppre5 = periph_prescaler_to_value(config.apb5.to_bits());
331 331
332 // enable all peripherals in sleep mode
333 enable_low_power_peripherals();
334
335 // enable interrupts
336 unsafe {
337 core::arch::asm!("cpsie i");
338 }
339
332 ClocksOutput { 340 ClocksOutput {
333 sysclk, 341 sysclk,
334 cpuclk, 342 cpuclk,
@@ -341,6 +349,183 @@ fn init_clocks(config: Config, input: &ClocksInput) -> ClocksOutput {
341 } 349 }
342} 350}
343 351
352fn enable_low_power_peripherals() {
353 // AHB1-5
354 RCC.ahb1lpenr().modify(|w| {
355 w.set_adc12lpen(true);
356 w.set_gpdma1lpen(true);
357 });
358 RCC.ahb2lpenr().modify(|w| {
359 w.set_adf1lpen(true);
360 w.set_mdf1lpen(true);
361 w.set_ramcfglpen(true);
362 });
363 RCC.ahb3lpenr().modify(|w| {
364 w.set_risaflpen(true);
365 w.set_iaclpen(true);
366 w.set_rifsclpen(true);
367 w.set_pkalpen(true);
368 w.set_saeslpen(true);
369 w.set_cryplpen(true);
370 w.set_hashlpen(true);
371 w.set_rnglpen(true);
372 });
373 RCC.ahb4lpenr().modify(|w| {
374 w.set_crclpen(true);
375 w.set_pwrlpen(true);
376 w.set_gpioqlpen(true);
377 w.set_gpioplpen(true);
378 w.set_gpioolpen(true);
379 w.set_gpionlpen(true);
380 w.set_gpiohlpen(true);
381 w.set_gpioglpen(true);
382 w.set_gpioflpen(true);
383 w.set_gpioelpen(true);
384 w.set_gpiodlpen(true);
385 w.set_gpioclpen(true);
386 w.set_gpioblpen(true);
387 w.set_gpioalpen(true);
388 });
389 RCC.ahb5lpenr().modify(|w| {
390 w.set_npulpen(true);
391 w.set_npucachelpen(true);
392 w.set_otg2lpen(true);
393 w.set_otgphy2lpen(true);
394 w.set_otgphy1lpen(true);
395 w.set_otg1lpen(true);
396 w.set_eth1lpen(true);
397 w.set_eth1rxlpen(true);
398 w.set_eth1txlpen(true);
399 w.set_eth1maclpen(true);
400 w.set_gpulpen(true);
401 w.set_gfxmmulpen(true);
402 w.set_mce4lpen(true);
403 w.set_xspi3lpen(true);
404 w.set_mce3lpen(true);
405 w.set_mce2lpen(true);
406 w.set_mce1lpen(true);
407 w.set_xspimlpen(true);
408 w.set_xspi2lpen(true);
409 w.set_sdmmc1lpen(true);
410 w.set_sdmmc2lpen(true);
411 w.set_pssilpen(true);
412 w.set_xspi1lpen(true);
413 w.set_fmclpen(true);
414 w.set_jpeglpen(true);
415 w.set_dma2dlpen(true);
416 w.set_hpdma1lpen(true);
417 });
418
419 // APB1-5
420 RCC.apb1llpenr().modify(|w| {
421 w.set_uart8lpen(true);
422 w.set_uart7lpen(true);
423 w.set_i3c2lpen(true);
424 w.set_i3c1lpen(true);
425 w.set_i2c3lpen(true);
426 w.set_i2c2lpen(true);
427 w.set_i2c1lpen(true);
428 w.set_uart5lpen(true);
429 w.set_uart4lpen(true);
430 w.set_usart3lpen(true);
431 w.set_usart2lpen(true);
432 w.set_spdifrx1lpen(true);
433 w.set_spi3lpen(true);
434 w.set_spi2lpen(true);
435 w.set_tim11lpen(true);
436 w.set_tim10lpen(true);
437 w.set_wwdglpen(true);
438 w.set_lptim1lpen(true);
439 w.set_tim14lpen(true);
440 w.set_tim13lpen(true);
441 w.set_tim12lpen(true);
442 w.set_tim7lpen(true);
443 w.set_tim6lpen(true);
444 w.set_tim5lpen(true);
445 w.set_tim4lpen(true);
446 w.set_tim3lpen(true);
447 w.set_tim2lpen(true);
448 });
449 RCC.apb1hlpenr().modify(|w| {
450 w.set_ucpd1lpen(true);
451 w.set_fdcanlpen(true);
452 w.set_mdioslpen(true);
453 });
454 RCC.apb2lpenr().modify(|w| {
455 w.set_sai2lpen(true);
456 w.set_sai1lpen(true);
457 w.set_spi5lpen(true);
458 w.set_tim9lpen(true);
459 w.set_tim17lpen(true);
460 w.set_tim16lpen(true);
461 w.set_tim15lpen(true);
462 w.set_tim18lpen(true);
463 w.set_spi4lpen(true);
464 w.set_spi1lpen(true);
465 w.set_usart10lpen(true);
466 w.set_uart9lpen(true);
467 w.set_usart6lpen(true);
468 w.set_usart1lpen(true);
469 w.set_tim8lpen(true);
470 w.set_tim1lpen(true);
471 });
472 RCC.apb3lpenr().modify(|w| {
473 w.set_dftlpen(true);
474 });
475 RCC.apb4llpenr().modify(|w| {
476 w.set_rtcapblpen(true);
477 w.set_rtclpen(true);
478 w.set_vrefbuflpen(true);
479 w.set_lptim5lpen(true);
480 w.set_lptim4lpen(true);
481 w.set_lptim3lpen(true);
482 w.set_lptim2lpen(true);
483 w.set_i2c4lpen(true);
484 w.set_spi6lpen(true);
485 w.set_lpuart1lpen(true);
486 w.set_hdplpen(true);
487 });
488 RCC.apb4hlpenr().modify(|w| {
489 w.set_dtslpen(true);
490 w.set_bseclpen(true);
491 w.set_syscfglpen(true);
492 });
493 RCC.apb5lpenr().modify(|w| {
494 w.set_csilpen(true);
495 w.set_venclpen(true);
496 w.set_gfxtimlpen(true);
497 w.set_dcmilpen(true);
498 w.set_ltdclpen(true);
499 });
500
501 RCC.buslpenr().modify(|w| {
502 w.set_aclknclpen(true);
503 w.set_aclknlpen(true);
504 });
505
506 RCC.memlpenr().modify(|w| {
507 w.set_bootromlpen(true);
508 w.set_vencramlpen(true);
509 w.set_npucacheramlpen(true);
510 w.set_flexramlpen(true);
511 w.set_axisram2lpen(true);
512 w.set_axisram1lpen(true);
513 w.set_bkpsramlpen(true);
514 w.set_ahbsram2lpen(true);
515 w.set_ahbsram1lpen(true);
516 w.set_axisram6lpen(true);
517 w.set_axisram5lpen(true);
518 w.set_axisram4lpen(true);
519 w.set_axisram3lpen(true);
520 });
521
522 RCC.misclpenr().modify(|w| {
523 w.set_perlpen(true);
524 w.set_xspiphycomplpen(true);
525 w.set_dbglpen(true);
526 });
527}
528
344const fn periph_prescaler_to_value(bits: u8) -> u8 { 529const fn periph_prescaler_to_value(bits: u8) -> u8 {
345 match bits { 530 match bits {
346 0 => 1, 531 0 => 1,