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authorDavid Lenfesty <[email protected]>2022-04-24 20:46:11 -0600
committerDario Nieuwenhuis <[email protected]>2022-04-30 04:49:24 +0200
commit0d2ef1099b67d92586099966450d8f4db19e72a4 (patch)
treea3ff210bba35af81e9c800cd6a5d73bb8f02d9f6
parentf30e5d2d3f57edb8263fb969a88ae242ea6d8f76 (diff)
initial work porting eth to f107
-rw-r--r--embassy-stm32/src/eth/v1a/mod.rs21
1 files changed, 12 insertions, 9 deletions
diff --git a/embassy-stm32/src/eth/v1a/mod.rs b/embassy-stm32/src/eth/v1a/mod.rs
index 8abe2e172..361a8f0ed 100644
--- a/embassy-stm32/src/eth/v1a/mod.rs
+++ b/embassy-stm32/src/eth/v1a/mod.rs
@@ -12,7 +12,7 @@ use embassy_net::{Device, DeviceCapabilities, LinkState, PacketBuf, MTU};
12 12
13use crate::gpio::sealed::Pin as __GpioPin; 13use crate::gpio::sealed::Pin as __GpioPin;
14use crate::gpio::{sealed::AFType, AnyPin, Speed}; 14use crate::gpio::{sealed::AFType, AnyPin, Speed};
15use crate::pac::{ETH, RCC, SYSCFG}; 15use crate::pac::{AFIO, ETH, RCC};
16 16
17mod descriptors; 17mod descriptors;
18mod rx_desc; 18mod rx_desc;
@@ -47,8 +47,9 @@ macro_rules! config_pins {
47 // NOTE(unsafe) Exclusive access to the registers 47 // NOTE(unsafe) Exclusive access to the registers
48 critical_section::with(|_| { 48 critical_section::with(|_| {
49 $( 49 $(
50 // TODO double check to ensure speed set *isn't required. This call *seems* to set
51 // GPIO to max speed.
50 $pin.set_as_af($pin.af_num(), AFType::OutputPushPull); 52 $pin.set_as_af($pin.af_num(), AFType::OutputPushPull);
51 $pin.set_speed(Speed::VeryHigh);
52 )* 53 )*
53 }) 54 })
54 }; 55 };
@@ -78,15 +79,17 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T,
78 // Enable the necessary Clocks 79 // Enable the necessary Clocks
79 // NOTE(unsafe) We have exclusive access to the registers 80 // NOTE(unsafe) We have exclusive access to the registers
80 critical_section::with(|_| { 81 critical_section::with(|_| {
81 RCC.apb2enr().modify(|w| w.set_syscfgen(true)); 82 RCC.apb2enr().modify(|w| w.set_afioen(true));
82 RCC.ahb1enr().modify(|w| { 83 RCC.ahbenr().modify(|w| {
83 w.set_ethen(true); 84 w.set_ethmacen(true);
84 w.set_ethtxen(true); 85 w.set_ethmactxen(true);
85 w.set_ethrxen(true); 86 w.set_ethmacrxen(true);
86 }); 87 });
87 88
88 // RMII (Reduced Media Independent Interface) 89 // Select RMII (Reduced Media Independent Interface)
89 SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(true)); 90 AFIO.mapr().modify(|w| w.set_mii_rmii_sel(true));
91
92 // TODO set MCO to eth clk
90 }); 93 });
91 94
92 config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en); 95 config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);