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authorMathis Deroo <[email protected]>2025-12-08 13:29:16 -0800
committerMathis Deroo <[email protected]>2025-12-09 10:52:10 -0800
commit0da28a271816b319c142254cb3598fd14096813a (patch)
tree760c50e5f9dd0b7017b4238f0b0c36c7b9dba4ce
parentb9bb7c0ebdbe19832ed9e9d75b12df86523c5fd2 (diff)
Remove duplication of interrupt trait and use embassy_hal_internal
Signed-off-by: Mathis Deroo <[email protected]>
-rw-r--r--embassy-mcxa/src/interrupt.rs151
-rw-r--r--embassy-mcxa/src/lib.rs8
2 files changed, 0 insertions, 159 deletions
diff --git a/embassy-mcxa/src/interrupt.rs b/embassy-mcxa/src/interrupt.rs
index 7eabc6495..725f8d499 100644
--- a/embassy-mcxa/src/interrupt.rs
+++ b/embassy-mcxa/src/interrupt.rs
@@ -282,157 +282,6 @@ impl InterruptExt for Rtc {
282 cortex_m::peripheral::NVIC::is_pending(Interrupt::RTC) 282 cortex_m::peripheral::NVIC::is_pending(Interrupt::RTC)
283 } 283 }
284} 284}
285pub struct Adc0;
286pub const ADC0: Adc0 = Adc0;
287
288impl InterruptExt for Adc0 {
289 /// Clear any pending ADC0 in NVIC.
290 #[inline]
291 fn unpend(&self) {
292 cortex_m::peripheral::NVIC::unpend(Interrupt::ADC0);
293 }
294
295 /// Set NVIC priority for ADC0.
296 #[inline]
297 fn set_priority(&self, priority: Priority) {
298 unsafe {
299 let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
300 nvic.set_priority(Interrupt::ADC0, u8::from(priority));
301 }
302 }
303
304 /// Enable ADC0 in NVIC.
305 #[inline]
306 unsafe fn enable(&self) {
307 cortex_m::peripheral::NVIC::unmask(Interrupt::ADC0);
308 }
309
310 /// Disable ADC0 in NVIC.
311 #[inline]
312 unsafe fn disable(&self) {
313 cortex_m::peripheral::NVIC::mask(Interrupt::ADC0);
314 }
315
316 /// Check if ADC0 is pending in NVIC.
317 #[inline]
318 fn is_pending(&self) -> bool {
319 cortex_m::peripheral::NVIC::is_pending(Interrupt::ADC0)
320 }
321}
322
323pub struct Adc1;
324pub const ADC1: Adc1 = Adc1;
325
326impl InterruptExt for Adc1 {
327 /// Clear any pending ADC1 in NVIC.
328 #[inline]
329 fn unpend(&self) {
330 cortex_m::peripheral::NVIC::unpend(Interrupt::ADC1);
331 }
332
333 /// Set NVIC priority for ADC1.
334 #[inline]
335 fn set_priority(&self, priority: Priority) {
336 unsafe {
337 let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
338 nvic.set_priority(Interrupt::ADC1, u8::from(priority));
339 }
340 }
341
342 /// Enable ADC1 in NVIC.
343 #[inline]
344 unsafe fn enable(&self) {
345 cortex_m::peripheral::NVIC::unmask(Interrupt::ADC1);
346 }
347
348 /// Disable ADC1 in NVIC.
349 #[inline]
350 unsafe fn disable(&self) {
351 cortex_m::peripheral::NVIC::mask(Interrupt::ADC1);
352 }
353
354 /// Check if ADC1 is pending in NVIC.
355 #[inline]
356 fn is_pending(&self) -> bool {
357 cortex_m::peripheral::NVIC::is_pending(Interrupt::ADC1)
358 }
359}
360
361pub struct Adc2;
362pub const ADC2: Adc2 = Adc2;
363
364impl InterruptExt for Adc2 {
365 /// Clear any pending ADC2 in NVIC.
366 #[inline]
367 fn unpend(&self) {
368 cortex_m::peripheral::NVIC::unpend(Interrupt::ADC2);
369 }
370
371 /// Set NVIC priority for ADC2.
372 #[inline]
373 fn set_priority(&self, priority: Priority) {
374 unsafe {
375 let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
376 nvic.set_priority(Interrupt::ADC2, u8::from(priority));
377 }
378 }
379
380 /// Enable ADC2 in NVIC.
381 #[inline]
382 unsafe fn enable(&self) {
383 cortex_m::peripheral::NVIC::unmask(Interrupt::ADC2);
384 }
385
386 /// Disable ADC2 in NVIC.
387 #[inline]
388 unsafe fn disable(&self) {
389 cortex_m::peripheral::NVIC::mask(Interrupt::ADC2);
390 }
391
392 /// Check if ADC2 is pending in NVIC.
393 #[inline]
394 fn is_pending(&self) -> bool {
395 cortex_m::peripheral::NVIC::is_pending(Interrupt::ADC2)
396 }
397}
398
399pub struct Adc3;
400pub const ADC3: Adc3 = Adc3;
401
402impl InterruptExt for Adc3 {
403 /// Clear any pending ADC3 in NVIC.
404 #[inline]
405 fn unpend(&self) {
406 cortex_m::peripheral::NVIC::unpend(Interrupt::ADC3);
407 }
408
409 /// Set NVIC priority for ADC3.
410 #[inline]
411 fn set_priority(&self, priority: Priority) {
412 unsafe {
413 let mut nvic = cortex_m::peripheral::Peripherals::steal().NVIC;
414 nvic.set_priority(Interrupt::ADC3, u8::from(priority));
415 }
416 }
417
418 /// Enable ADC3 in NVIC.
419 #[inline]
420 unsafe fn enable(&self) {
421 cortex_m::peripheral::NVIC::unmask(Interrupt::ADC3);
422 }
423
424 /// Disable ADC3 in NVIC.
425 #[inline]
426 unsafe fn disable(&self) {
427 cortex_m::peripheral::NVIC::mask(Interrupt::ADC3);
428 }
429
430 /// Check if ADC3 is pending in NVIC.
431 #[inline]
432 fn is_pending(&self) -> bool {
433 cortex_m::peripheral::NVIC::is_pending(Interrupt::ADC3)
434 }
435}
436 285
437pub struct Gpio0; 286pub struct Gpio0;
438pub const GPIO0: Gpio0 = Gpio0; 287pub const GPIO0: Gpio0 = Gpio0;
diff --git a/embassy-mcxa/src/lib.rs b/embassy-mcxa/src/lib.rs
index 10b6167b6..be279e509 100644
--- a/embassy-mcxa/src/lib.rs
+++ b/embassy-mcxa/src/lib.rs
@@ -354,14 +354,6 @@ pub fn init(cfg: crate::config::Config) -> Peripherals {
354 // Apply user-configured priority early; enabling is left to examples/apps 354 // Apply user-configured priority early; enabling is left to examples/apps
355 crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority); 355 crate::interrupt::RTC.set_priority(cfg.rtc_interrupt_priority);
356 // Apply user-configured priority early; enabling is left to examples/apps 356 // Apply user-configured priority early; enabling is left to examples/apps
357 crate::interrupt::ADC0.set_priority(cfg.adc_interrupt_priority);
358 // Apply user-configured priority early; enabling is left to examples/apps
359 crate::interrupt::ADC1.set_priority(cfg.adc_interrupt_priority);
360 // Apply user-configured priority early; enabling is left to examples/apps
361 crate::interrupt::ADC2.set_priority(cfg.adc_interrupt_priority);
362 // Apply user-configured priority early; enabling is left to examples/apps
363 crate::interrupt::ADC3.set_priority(cfg.adc_interrupt_priority);
364 // Apply user-configured priority early; enabling is left to examples/apps
365 crate::interrupt::GPIO0.set_priority(cfg.gpio_interrupt_priority); 357 crate::interrupt::GPIO0.set_priority(cfg.gpio_interrupt_priority);
366 // Apply user-configured priority early; enabling is left to examples/apps 358 // Apply user-configured priority early; enabling is left to examples/apps
367 crate::interrupt::GPIO1.set_priority(cfg.gpio_interrupt_priority); 359 crate::interrupt::GPIO1.set_priority(cfg.gpio_interrupt_priority);