More support for U5 PWR (ish), RCC, and FLASH (ish).

2 files changed, 2 insertions, 9 deletions

diff --git a/embassy-stm32/src/pwr/u5.rs b/embassy-stm32/src/pwr/u5.rs
index b4b01ea39..a90659d9c 100644
--- a/embassy-stm32/src/pwr/u5.rs
+++ b/embassy-stm32/src/pwr/u5.rs
@@ -1,4 +1,3 @@
-use crate::pac::{PWR, RCC, SYSCFG};
 use crate::peripherals;
 
 /// Voltage Scale
diff --git a/embassy-stm32/src/rcc/u5/mod.rs b/embassy-stm32/src/rcc/u5/mod.rs
index 0087f6993..6e68b2205 100644
--- a/embassy-stm32/src/rcc/u5/mod.rs
+++ b/embassy-stm32/src/rcc/u5/mod.rs
@@ -1,7 +1,7 @@
 use crate::pac;
 use crate::peripherals::{self, RCC};
 use crate::pwr::{Power, VoltageScale};
-use crate::rcc::{get_freqs, set_freqs, Clocks};
+use crate::rcc::{set_freqs, Clocks};
 use crate::time::{Hertz, U32Ext};
 use stm32_metapac::rcc::vals::{Hpre, Msirange, Msirgsel, Pllm, Pllsrc, Ppre, Sw};
 
@@ -108,12 +108,6 @@ pub enum PllM {
     Div16 = 0b1111,
 }
 
-impl PllM {
-    fn to_div(&self) -> u32 {
-        (*self as u32) + 1
-    }
-}
-
 impl Into<Pllm> for PllM {
     fn into(self) -> Pllm {
         Pllm(self as u8)
@@ -490,7 +484,7 @@ impl RccExt for RCC {
             }
         };
 
-        let (apb3_freq, apb3_tim_freq) = match cfgr.apb3_pre {
+        let (apb3_freq, _apb3_tim_freq) = match cfgr.apb3_pre {
             APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
             pre => {
                 let pre: u8 = pre.into();