aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorxoviat <[email protected]>2021-03-04 17:27:46 -0600
committerxoviat <[email protected]>2021-03-04 17:27:46 -0600
commit13f6c47a88d8335a59c66a4a2e3a9227f3c55e6d (patch)
tree17574fc3ed9d5ee43934b7b2f10cc3c194d3ddcb
parent9bcb0c36dc23c3faa946296e9ee05a073f6d2882 (diff)
impl. stm32f405
-rw-r--r--embassy-stm32f4/src/serial.rs2
1 files changed, 2 insertions, 0 deletions
diff --git a/embassy-stm32f4/src/serial.rs b/embassy-stm32f4/src/serial.rs
index 36d569a9e..36ca5af56 100644
--- a/embassy-stm32f4/src/serial.rs
+++ b/embassy-stm32f4/src/serial.rs
@@ -217,6 +217,7 @@ macro_rules! usart {
217 } 217 }
218} 218}
219 219
220#[cfg(any(feature = "stm32f405",))]
220dma! { 221dma! {
221 DMA2_STREAM0 => (DMA2, Stream0), 222 DMA2_STREAM0 => (DMA2, Stream0),
222 DMA2_STREAM1 => (DMA2, Stream1), 223 DMA2_STREAM1 => (DMA2, Stream1),
@@ -235,6 +236,7 @@ dma! {
235 DMA1_STREAM6 => (DMA1, Stream6), 236 DMA1_STREAM6 => (DMA1, Stream6),
236} 237}
237 238
239#[cfg(any(feature = "stm32f405",))]
238usart! { 240usart! {
239 USART1 => (USART1), 241 USART1 => (USART1),
240 USART2 => (USART2), 242 USART2 => (USART2),