Merge pull request #3688 from klownfish/u5_adc

STM32U5: Add ADC drivers

7 files changed, 686 insertions, 22 deletions

diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index ffd9a67e7..f35271016 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -73,7 +73,7 @@ rand_core = "0.6.3"
 sdio-host = "0.5.0"
 critical-section = "1.1"
 #stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ddb0e7abab14bf3e1399875767b8834442382988" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-392e41259ffc5ffbfd79169ee80451114fb367fe" }
 
 vcell = "0.1.3"
 nb = "1.0.0"
@@ -102,7 +102,7 @@ proc-macro2 = "1.0.36"
 quote = "1.0.15"
 
 #stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ddb0e7abab14bf3e1399875767b8834442382988", default-features = false, features = ["metadata"] }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-392e41259ffc5ffbfd79169ee80451114fb367fe", default-features = false, features = ["metadata"] }
 
 [features]
 default = ["rt"]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index f92d8b8ba..e293cf965 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -1238,13 +1238,12 @@ fn main() {
     // ========
     // Generate dma_trait_impl!
 
-    let signals: HashMap<_, _> = [
+    let mut signals: HashMap<_, _> = [
         // (kind, signal) => trait
         (("adc", "ADC"), quote!(crate::adc::RxDma)),
         (("adc", "ADC1"), quote!(crate::adc::RxDma)),
         (("adc", "ADC2"), quote!(crate::adc::RxDma)),
         (("adc", "ADC3"), quote!(crate::adc::RxDma)),
-        (("adc", "ADC4"), quote!(crate::adc::RxDma)),
         (("ucpd", "RX"), quote!(crate::ucpd::RxDma)),
         (("ucpd", "TX"), quote!(crate::ucpd::TxDma)),
         (("usart", "RX"), quote!(crate::usart::RxDma)),
@@ -1279,6 +1278,12 @@ fn main() {
     ]
     .into();
 
+    if chip_name.starts_with("stm32u5") {
+        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma4));
+    } else {
+        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma));
+    }
+
     for p in METADATA.peripherals {
         if let Some(regs) = &p.registers {
             // FIXME: stm32u5a crash on Cordic driver
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 4ab82c1d9..36898b8f9 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -4,7 +4,7 @@
 #![allow(missing_docs)] // TODO
 #![cfg_attr(adc_f3_v2, allow(unused))]
 
-#[cfg(not(any(adc_f3_v2, adc_u5)))]
+#[cfg(not(any(adc_f3_v2)))]
 #[cfg_attr(adc_f1, path = "f1.rs")]
 #[cfg_attr(adc_f3, path = "f3.rs")]
 #[cfg_attr(adc_f3_v1_1, path = "f3_v1_1.rs")]
@@ -12,33 +12,37 @@
 #[cfg_attr(adc_l0, path = "v1.rs")]
 #[cfg_attr(adc_v2, path = "v2.rs")]
 #[cfg_attr(any(adc_v3, adc_g0, adc_h5, adc_u0), path = "v3.rs")]
-#[cfg_attr(adc_v4, path = "v4.rs")]
+#[cfg_attr(any(adc_v4, adc_u5), path = "v4.rs")]
 #[cfg_attr(adc_g4, path = "g4.rs")]
 mod _version;
 
 use core::marker::PhantomData;
 
 #[allow(unused)]
-#[cfg(not(any(adc_f3_v2, adc_u5)))]
+#[cfg(not(any(adc_f3_v2)))]
 pub use _version::*;
 #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
 use embassy_sync::waitqueue::AtomicWaker;
 
-#[cfg(not(any(adc_u5)))]
+#[cfg(adc_u5)]
+#[path = "u5_adc4.rs"]
+pub mod adc4;
+
 pub use crate::pac::adc::vals;
-#[cfg(not(any(adc_f1, adc_f3_v2, adc_u5)))]
+#[cfg(not(any(adc_f1, adc_f3_v2)))]
 pub use crate::pac::adc::vals::Res as Resolution;
-#[cfg(not(any(adc_u5)))]
 pub use crate::pac::adc::vals::SampleTime;
 use crate::peripherals;
 
 dma_trait!(RxDma, Instance);
+#[cfg(adc_u5)]
+dma_trait!(RxDma4, adc4::Instance);
 
 /// Analog to Digital driver.
 pub struct Adc<'d, T: Instance> {
     #[allow(unused)]
     adc: crate::PeripheralRef<'d, T>,
-    #[cfg(not(any(adc_f3_v2, adc_f3_v1_1, adc_u5)))]
+    #[cfg(not(any(adc_f3_v2, adc_f3_v1_1)))]
     sample_time: SampleTime,
 }
 
@@ -59,7 +63,7 @@ impl State {
 trait SealedInstance {
     #[allow(unused)]
     fn regs() -> crate::pac::adc::Adc;
-    #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0, adc_u5)))]
+    #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
     #[allow(unused)]
     fn common_regs() -> crate::pac::adccommon::AdcCommon;
     #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
@@ -67,7 +71,7 @@ trait SealedInstance {
 }
 
 pub(crate) trait SealedAdcChannel<T> {
-    #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4))]
+    #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5))]
     fn setup(&mut self) {}
 
     #[allow(unused)]
@@ -101,7 +105,8 @@ pub(crate) fn blocking_delay_us(us: u32) {
     adc_f3_v1_1,
     adc_g0,
     adc_u0,
-    adc_h5
+    adc_h5,
+    adc_u5
 )))]
 #[allow(private_bounds)]
 pub trait Instance: SealedInstance + crate::Peripheral<P = Self> {
@@ -120,7 +125,8 @@ pub trait Instance: SealedInstance + crate::Peripheral<P = Self> {
     adc_f3_v1_1,
     adc_g0,
     adc_u0,
-    adc_h5
+    adc_h5,
+    adc_u5
 ))]
 #[allow(private_bounds)]
 pub trait Instance: SealedInstance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {
@@ -132,7 +138,7 @@ pub trait Instance: SealedInstance + crate::Peripheral<P = Self> + crate::rcc::R
 pub trait AdcChannel<T>: SealedAdcChannel<T> + Sized {
     #[allow(unused_mut)]
     fn degrade_adc(mut self) -> AnyAdcChannel<T> {
-        #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4))]
+        #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5))]
         self.setup();
 
         AnyAdcChannel {
@@ -158,6 +164,38 @@ impl<T: Instance> SealedAdcChannel<T> for AnyAdcChannel<T> {
     }
 }
 
+#[cfg(adc_u5)]
+foreach_adc!(
+    (ADC4, $common_inst:ident, $clock:ident) => {
+        impl crate::adc::adc4::SealedInstance for peripherals::ADC4 {
+            fn regs() -> crate::pac::adc::Adc4 {
+                crate::pac::ADC4
+            }
+        }
+
+        impl crate::adc::adc4::Instance for peripherals::ADC4 {
+            type Interrupt = crate::_generated::peripheral_interrupts::ADC4::GLOBAL;
+        }
+    };
+
+    ($inst:ident, $common_inst:ident, $clock:ident) => {
+        impl crate::adc::SealedInstance for peripherals::$inst {
+            fn regs() -> crate::pac::adc::Adc {
+                crate::pac::$inst
+            }
+
+            fn common_regs() -> crate::pac::adccommon::AdcCommon {
+                return crate::pac::$common_inst
+            }
+        }
+
+        impl crate::adc::Instance for peripherals::$inst {
+            type Interrupt = crate::_generated::peripheral_interrupts::$inst::GLOBAL;
+        }
+    };
+);
+
+#[cfg(not(adc_u5))]
 foreach_adc!(
     ($inst:ident, $common_inst:ident, $clock:ident) => {
         impl crate::adc::SealedInstance for peripherals::$inst {
@@ -165,7 +203,7 @@ foreach_adc!(
                 crate::pac::$inst
             }
 
-            #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0, adc_u5)))]
+            #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
             fn common_regs() -> crate::pac::adccommon::AdcCommon {
                 return crate::pac::$common_inst
             }
@@ -187,7 +225,7 @@ macro_rules! impl_adc_pin {
     ($inst:ident, $pin:ident, $ch:expr) => {
         impl crate::adc::AdcChannel<peripherals::$inst> for crate::peripherals::$pin {}
         impl crate::adc::SealedAdcChannel<peripherals::$inst> for crate::peripherals::$pin {
-            #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4))]
+            #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5))]
             fn setup(&mut self) {
                 <Self as crate::gpio::SealedPin>::set_as_analog(self);
             }
@@ -202,12 +240,12 @@ macro_rules! impl_adc_pin {
 /// Get the maximum reading value for this resolution.
 ///
 /// This is `2**n - 1`.
-#[cfg(not(any(adc_f1, adc_f3_v2, adc_u5)))]
+#[cfg(not(any(adc_f1, adc_f3_v2)))]
 pub const fn resolution_to_max_count(res: Resolution) -> u32 {
     match res {
         #[cfg(adc_v4)]
         Resolution::BITS16 => (1 << 16) - 1,
-        #[cfg(adc_v4)]
+        #[cfg(any(adc_v4, adc_u5))]
         Resolution::BITS14 => (1 << 14) - 1,
         #[cfg(adc_v4)]
         Resolution::BITS14V => (1 << 14) - 1,
diff --git a/embassy-stm32/src/adc/u5_adc4.rs b/embassy-stm32/src/adc/u5_adc4.rs
new file mode 100644
index 000000000..0635dad9b
--- /dev/null
+++ b/embassy-stm32/src/adc/u5_adc4.rs
@@ -0,0 +1,479 @@
+#[allow(unused)]
+use pac::adc::vals::{Adc4Dmacfg, Adc4Exten, Adc4OversamplingRatio};
+
+use super::{blocking_delay_us, AdcChannel, AnyAdcChannel, RxDma4, SealedAdcChannel};
+use crate::dma::Transfer;
+pub use crate::pac::adc::regs::Adc4Chselrmod0;
+pub use crate::pac::adc::vals::{Adc4Presc as Presc, Adc4Res as Resolution, Adc4SampleTime as SampleTime};
+use crate::time::Hertz;
+use crate::{pac, rcc, Peripheral};
+
+const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
+
+/// Default VREF voltage used for sample conversion to millivolts.
+pub const VREF_DEFAULT_MV: u32 = 3300;
+/// VREF voltage used for factory calibration of VREFINTCAL register.
+pub const VREF_CALIB_MV: u32 = 3300;
+
+const VREF_CHANNEL: u8 = 0;
+const VCORE_CHANNEL: u8 = 12;
+const TEMP_CHANNEL: u8 = 13;
+const VBAT_CHANNEL: u8 = 14;
+const DAC_CHANNEL: u8 = 21;
+
+// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
+/// Internal voltage reference channel.
+pub struct VrefInt;
+impl<T: Instance> AdcChannel<T> for VrefInt {}
+impl<T: Instance> SealedAdcChannel<T> for VrefInt {
+    fn channel(&self) -> u8 {
+        VREF_CHANNEL
+    }
+}
+
+/// Internal temperature channel.
+pub struct Temperature;
+impl<T: Instance> AdcChannel<T> for Temperature {}
+impl<T: Instance> SealedAdcChannel<T> for Temperature {
+    fn channel(&self) -> u8 {
+        TEMP_CHANNEL
+    }
+}
+
+/// Internal battery voltage channel.
+pub struct Vbat;
+impl<T: Instance> AdcChannel<T> for Vbat {}
+impl<T: Instance> SealedAdcChannel<T> for Vbat {
+    fn channel(&self) -> u8 {
+        VBAT_CHANNEL
+    }
+}
+
+/// Internal DAC channel.
+pub struct Dac;
+impl<T: Instance> AdcChannel<T> for Dac {}
+impl<T: Instance> SealedAdcChannel<T> for Dac {
+    fn channel(&self) -> u8 {
+        DAC_CHANNEL
+    }
+}
+
+/// Internal Vcore channel.
+pub struct Vcore;
+impl<T: Instance> AdcChannel<T> for Vcore {}
+impl<T: Instance> SealedAdcChannel<T> for Vcore {
+    fn channel(&self) -> u8 {
+        VCORE_CHANNEL
+    }
+}
+
+pub enum DacChannel {
+    OUT1,
+    OUT2,
+}
+
+/// Number of samples used for averaging.
+pub enum Averaging {
+    Disabled,
+    Samples2,
+    Samples4,
+    Samples8,
+    Samples16,
+    Samples32,
+    Samples64,
+    Samples128,
+    Samples256,
+}
+
+pub const fn resolution_to_max_count(res: Resolution) -> u32 {
+    match res {
+        Resolution::BITS12 => (1 << 12) - 1,
+        Resolution::BITS10 => (1 << 10) - 1,
+        Resolution::BITS8 => (1 << 8) - 1,
+        Resolution::BITS6 => (1 << 6) - 1,
+        #[allow(unreachable_patterns)]
+        _ => core::unreachable!(),
+    }
+}
+
+// NOTE (unused): The prescaler enum closely copies the hardware capabilities,
+// but high prescaling doesn't make a lot of sense in the current implementation and is ommited.
+#[allow(unused)]
+enum Prescaler {
+    NotDivided,
+    DividedBy2,
+    DividedBy4,
+    DividedBy6,
+    DividedBy8,
+    DividedBy10,
+    DividedBy12,
+    DividedBy16,
+    DividedBy32,
+    DividedBy64,
+    DividedBy128,
+    DividedBy256,
+}
+
+impl Prescaler {
+    fn from_ker_ck(frequency: Hertz) -> Self {
+        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
+        match raw_prescaler {
+            0 => Self::NotDivided,
+            1 => Self::DividedBy2,
+            2..=3 => Self::DividedBy4,
+            4..=5 => Self::DividedBy6,
+            6..=7 => Self::DividedBy8,
+            8..=9 => Self::DividedBy10,
+            10..=11 => Self::DividedBy12,
+            _ => unimplemented!(),
+        }
+    }
+
+    fn divisor(&self) -> u32 {
+        match self {
+            Prescaler::NotDivided => 1,
+            Prescaler::DividedBy2 => 2,
+            Prescaler::DividedBy4 => 4,
+            Prescaler::DividedBy6 => 6,
+            Prescaler::DividedBy8 => 8,
+            Prescaler::DividedBy10 => 10,
+            Prescaler::DividedBy12 => 12,
+            Prescaler::DividedBy16 => 16,
+            Prescaler::DividedBy32 => 32,
+            Prescaler::DividedBy64 => 64,
+            Prescaler::DividedBy128 => 128,
+            Prescaler::DividedBy256 => 256,
+        }
+    }
+
+    fn presc(&self) -> Presc {
+        match self {
+            Prescaler::NotDivided => Presc::DIV1,
+            Prescaler::DividedBy2 => Presc::DIV2,
+            Prescaler::DividedBy4 => Presc::DIV4,
+            Prescaler::DividedBy6 => Presc::DIV6,
+            Prescaler::DividedBy8 => Presc::DIV8,
+            Prescaler::DividedBy10 => Presc::DIV10,
+            Prescaler::DividedBy12 => Presc::DIV12,
+            Prescaler::DividedBy16 => Presc::DIV16,
+            Prescaler::DividedBy32 => Presc::DIV32,
+            Prescaler::DividedBy64 => Presc::DIV64,
+            Prescaler::DividedBy128 => Presc::DIV128,
+            Prescaler::DividedBy256 => Presc::DIV256,
+        }
+    }
+}
+
+pub trait SealedInstance {
+    #[allow(unused)]
+    fn regs() -> crate::pac::adc::Adc4;
+}
+
+pub trait Instance: SealedInstance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {
+    type Interrupt: crate::interrupt::typelevel::Interrupt;
+}
+
+pub struct Adc4<'d, T: Instance> {
+    #[allow(unused)]
+    adc: crate::PeripheralRef<'d, T>,
+}
+
+#[derive(Debug)]
+pub enum Adc4Error {
+    InvalidSequence,
+    DMAError,
+}
+
+impl<'d, T: Instance> Adc4<'d, T> {
+    /// Create a new ADC driver.
+    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
+        embassy_hal_internal::into_ref!(adc);
+        rcc::enable_and_reset::<T>();
+        let prescaler = Prescaler::from_ker_ck(T::frequency());
+
+        T::regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+
+        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
+        info!("ADC4 frequency set to {} Hz", frequency.0);
+
+        if frequency > MAX_ADC_CLK_FREQ {
+            panic!("Maximal allowed frequency for ADC4 is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
+        }
+
+        let mut s = Self { adc };
+
+        s.power_up();
+
+        s.calibrate();
+        blocking_delay_us(1);
+
+        s.enable();
+        s.configure();
+
+        s
+    }
+
+    fn power_up(&mut self) {
+        T::regs().isr().modify(|w| {
+            w.set_ldordy(true);
+        });
+        T::regs().cr().modify(|w| {
+            w.set_advregen(true);
+        });
+        while !T::regs().isr().read().ldordy() {}
+
+        T::regs().isr().modify(|w| {
+            w.set_ldordy(true);
+        });
+    }
+
+    fn calibrate(&mut self) {
+        T::regs().cr().modify(|w| w.set_adcal(true));
+        while T::regs().cr().read().adcal() {}
+        T::regs().isr().modify(|w| w.set_eocal(true));
+    }
+
+    fn enable(&mut self) {
+        T::regs().isr().write(|w| w.set_adrdy(true));
+        T::regs().cr().modify(|w| w.set_aden(true));
+        while !T::regs().isr().read().adrdy() {}
+        T::regs().isr().write(|w| w.set_adrdy(true));
+    }
+
+    fn configure(&mut self) {
+        // single conversion mode, software trigger
+        T::regs().cfgr1().modify(|w| {
+            w.set_cont(false);
+            w.set_discen(false);
+            w.set_exten(Adc4Exten::DISABLED);
+            w.set_chselrmod(false);
+        });
+
+        // only use one channel at the moment
+        T::regs().smpr().modify(|w| {
+            for i in 0..24 {
+                w.set_smpsel(i, false);
+            }
+        });
+    }
+
+    /// Enable reading the voltage reference internal channel.
+    pub fn enable_vrefint(&self) -> VrefInt {
+        T::regs().ccr().modify(|w| {
+            w.set_vrefen(true);
+        });
+
+        VrefInt {}
+    }
+
+    /// Enable reading the temperature internal channel.
+    pub fn enable_temperature(&self) -> Temperature {
+        T::regs().ccr().modify(|w| {
+            w.set_vsensesel(true);
+        });
+
+        Temperature {}
+    }
+
+    /// Enable reading the vbat internal channel.
+    pub fn enable_vbat(&self) -> Vbat {
+        T::regs().ccr().modify(|w| {
+            w.set_vbaten(true);
+        });
+
+        Vbat {}
+    }
+
+    /// Enable reading the vbat internal channel.
+    pub fn enable_vcore(&self) -> Vcore {
+        Vcore {}
+    }
+
+    /// Enable reading the vbat internal channel.
+    pub fn enable_dac_channel(&self, dac: DacChannel) -> Dac {
+        let mux;
+        match dac {
+            DacChannel::OUT1 => mux = false,
+            DacChannel::OUT2 => mux = true,
+        }
+        T::regs().or().modify(|w| w.set_chn21sel(mux));
+        Dac {}
+    }
+
+    /// Set the ADC sample time.
+    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
+        T::regs().smpr().modify(|w| {
+            w.set_smp(0, sample_time);
+        });
+    }
+
+    /// Get the ADC sample time.
+    pub fn sample_time(&self) -> SampleTime {
+        T::regs().smpr().read().smp(0)
+    }
+
+    /// Set the ADC resolution.
+    pub fn set_resolution(&mut self, resolution: Resolution) {
+        T::regs().cfgr1().modify(|w| w.set_res(resolution.into()));
+    }
+
+    /// Set hardware averaging.
+    pub fn set_averaging(&mut self, averaging: Averaging) {
+        let (enable, samples, right_shift) = match averaging {
+            Averaging::Disabled => (false, Adc4OversamplingRatio::OVERSAMPLE2X, 0),
+            Averaging::Samples2 => (true, Adc4OversamplingRatio::OVERSAMPLE2X, 1),
+            Averaging::Samples4 => (true, Adc4OversamplingRatio::OVERSAMPLE4X, 2),
+            Averaging::Samples8 => (true, Adc4OversamplingRatio::OVERSAMPLE8X, 3),
+            Averaging::Samples16 => (true, Adc4OversamplingRatio::OVERSAMPLE16X, 4),
+            Averaging::Samples32 => (true, Adc4OversamplingRatio::OVERSAMPLE32X, 5),
+            Averaging::Samples64 => (true, Adc4OversamplingRatio::OVERSAMPLE64X, 6),
+            Averaging::Samples128 => (true, Adc4OversamplingRatio::OVERSAMPLE128X, 7),
+            Averaging::Samples256 => (true, Adc4OversamplingRatio::OVERSAMPLE256X, 8),
+        };
+
+        T::regs().cfgr2().modify(|w| {
+            w.set_ovsr(samples);
+            w.set_ovss(right_shift);
+            w.set_ovse(enable)
+        })
+    }
+
+    /// Read an ADC channel.
+    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+        channel.setup();
+
+        // Select channel
+        T::regs().chselrmod0().write_value(Adc4Chselrmod0(0_u32));
+        T::regs().chselrmod0().modify(|w| {
+            w.set_chsel(channel.channel() as usize, true);
+        });
+
+        // Reset interrupts
+        T::regs().isr().modify(|reg| {
+            reg.set_eos(true);
+            reg.set_eoc(true);
+        });
+
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+
+        while !T::regs().isr().read().eos() {
+            // spin
+        }
+
+        T::regs().dr().read().0 as u16
+    }
+
+    /// Read one or multiple ADC channels using DMA.
+    ///
+    /// `sequence` iterator and `readings` must have the same length.
+    /// The channels in `sequence` must be in ascending order.
+    ///
+    /// Example
+    /// ```rust,ignore
+    /// use embassy_stm32::adc::adc4;
+    /// use embassy_stm32::adc::AdcChannel;
+    ///
+    /// let mut adc4 = adc4::Adc4::new(p.ADC4);
+    /// let mut adc4_pin1 = p.PC1;
+    /// let mut adc4_pin2 = p.PC0;
+    /// let mut degraded41 = adc4_pin1.degrade_adc();
+    /// let mut degraded42 = adc4_pin2.degrade_adc();
+    /// let mut measurements = [0u16; 2];
+    /// // not that the channels must be in ascending order
+    /// adc4.read(
+    ///     &mut p.GPDMA1_CH1,
+    ///    [
+    ///        &mut degraded42,
+    ///        &mut degraded41,
+    ///    ]
+    ///    .into_iter(),
+    ///    &mut measurements,
+    /// ).await.unwrap();
+    /// ```
+    pub async fn read(
+        &mut self,
+        rx_dma: &mut impl RxDma4<T>,
+        sequence: impl ExactSizeIterator<Item = &mut AnyAdcChannel<T>>,
+        readings: &mut [u16],
+    ) -> Result<(), Adc4Error> {
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() == readings.len(),
+            "Sequence length must be equal to readings length"
+        );
+
+        // Ensure no conversions are ongoing
+        Self::cancel_conversions();
+
+        T::regs().isr().modify(|reg| {
+            reg.set_ovr(true);
+            reg.set_eos(true);
+            reg.set_eoc(true);
+        });
+
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_dmaen(true);
+            reg.set_dmacfg(Adc4Dmacfg::ONESHOT);
+            reg.set_chselrmod(false);
+        });
+
+        // Verify and activate sequence
+        let mut prev_channel: i16 = -1;
+        T::regs().chselrmod0().write_value(Adc4Chselrmod0(0_u32));
+        for channel in sequence {
+            let channel_num = channel.channel;
+            if channel_num as i16 <= prev_channel {
+                return Err(Adc4Error::InvalidSequence);
+            };
+            prev_channel = channel_num as i16;
+
+            T::regs().chselrmod0().modify(|w| {
+                w.set_chsel(channel.channel as usize, true);
+            });
+        }
+
+        let request = rx_dma.request();
+        let transfer = unsafe {
+            Transfer::new_read(
+                rx_dma,
+                request,
+                T::regs().dr().as_ptr() as *mut u16,
+                readings,
+                Default::default(),
+            )
+        };
+
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+
+        transfer.await;
+
+        // Ensure conversions are finished.
+        Self::cancel_conversions();
+
+        // Reset configuration.
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_dmaen(false);
+        });
+
+        if T::regs().isr().read().ovr() {
+            Err(Adc4Error::DMAError)
+        } else {
+            Ok(())
+        }
+    }
+
+    fn cancel_conversions() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(true);
+            });
+            while T::regs().cr().read().adstart() {}
+        }
+    }
+}
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index 63b5b58ea..46f9c7ac7 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -1,5 +1,7 @@
+#[cfg(not(stm32u5))]
+use pac::adc::vals::{Adcaldif, Boost};
 #[allow(unused)]
-use pac::adc::vals::{Adcaldif, Adstp, Boost, Difsel, Dmngt, Exten, Pcsel};
+use pac::adc::vals::{Adstp, Difsel, Dmngt, Exten, Pcsel};
 use pac::adccommon::vals::Presc;
 
 use super::{
@@ -19,6 +21,8 @@ pub const VREF_CALIB_MV: u32 = 3300;
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(60);
 #[cfg(stm32h7)]
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(50);
+#[cfg(stm32u5)]
+const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
 
 #[cfg(stm32g4)]
 const VREF_CHANNEL: u8 = 18;
@@ -31,8 +35,16 @@ const VREF_CHANNEL: u8 = 19;
 const TEMP_CHANNEL: u8 = 18;
 
 // TODO this should be 14 for H7a/b/35
+#[cfg(not(stm32u5))]
 const VBAT_CHANNEL: u8 = 17;
 
+#[cfg(stm32u5)]
+const VREF_CHANNEL: u8 = 0;
+#[cfg(stm32u5)]
+const TEMP_CHANNEL: u8 = 19;
+#[cfg(stm32u5)]
+const VBAT_CHANNEL: u8 = 18;
+
 // NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
 /// Internal voltage reference channel.
 pub struct VrefInt;
@@ -209,6 +221,7 @@ impl<'d, T: Instance> Adc<'d, T> {
 
     fn calibrate(&mut self) {
         T::regs().cr().modify(|w| {
+            #[cfg(not(adc_u5))]
             w.set_adcaldif(Adcaldif::SINGLEENDED);
             w.set_adcallin(true);
         });
@@ -446,7 +459,7 @@ impl<'d, T: Instance> Adc<'d, T> {
 
         Self::set_channel_sample_time(channel, sample_time);
 
-        #[cfg(stm32h7)]
+        #[cfg(any(stm32h7, stm32u5))]
         {
             T::regs().cfgr2().modify(|w| w.set_lshift(0));
             T::regs()
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 857090303..d04199d05 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -238,6 +238,10 @@ pub struct Config {
     #[cfg(any(stm32l4, stm32l5, stm32u5))]
     pub enable_independent_io_supply: bool,
 
+    /// On the U5 series all analog peripherals are powered by a separate supply.
+    #[cfg(stm32u5)]
+    pub enable_independent_analog_supply: bool,
+
     /// BDMA interrupt priority.
     ///
     /// Defaults to P0 (highest).
@@ -277,6 +281,8 @@ impl Default for Config {
             enable_debug_during_sleep: true,
             #[cfg(any(stm32l4, stm32l5, stm32u5))]
             enable_independent_io_supply: true,
+            #[cfg(stm32u5)]
+            enable_independent_analog_supply: true,
             #[cfg(bdma)]
             bdma_interrupt_priority: Priority::P0,
             #[cfg(dma)]
@@ -527,6 +533,20 @@ fn init_hw(config: Config) -> Peripherals {
             crate::pac::PWR.svmcr().modify(|w| {
                 w.set_io2sv(config.enable_independent_io_supply);
             });
+            if config.enable_independent_analog_supply {
+                crate::pac::PWR.svmcr().modify(|w| {
+                    w.set_avm1en(true);
+                });
+                while !crate::pac::PWR.svmsr().read().vdda1rdy() {}
+                crate::pac::PWR.svmcr().modify(|w| {
+                    w.set_asv(true);
+                });
+            } else {
+                crate::pac::PWR.svmcr().modify(|w| {
+                    w.set_avm1en(false);
+                    w.set_avm2en(false);
+                });
+            }
         }
 
         // dead battery functionality is still present on these
diff --git a/examples/stm32u5/src/bin/adc.rs b/examples/stm32u5/src/bin/adc.rs
new file mode 100644
index 000000000..6ba21cc63
--- /dev/null
+++ b/examples/stm32u5/src/bin/adc.rs
@@ -0,0 +1,109 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_stm32::adc;
+use embassy_stm32::adc::{adc4, AdcChannel};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: embassy_executor::Spawner) {
+    let config = embassy_stm32::Config::default();
+
+    let mut p = embassy_stm32::init(config);
+
+    // **** ADC1 init ****
+    let mut adc1 = adc::Adc::new(p.ADC1);
+    let mut adc1_pin1 = p.PA3; // A0 on nucleo u5a5
+    let mut adc1_pin2 = p.PA2; // A1
+    adc1.set_resolution(adc::Resolution::BITS14);
+    adc1.set_averaging(adc::Averaging::Samples1024);
+    adc1.set_sample_time(adc::SampleTime::CYCLES160_5);
+    let max1 = adc::resolution_to_max_count(adc::Resolution::BITS14);
+
+    // **** ADC2 init ****
+    let mut adc2 = adc::Adc::new(p.ADC2);
+    let mut adc2_pin1 = p.PC3; // A2
+    let mut adc2_pin2 = p.PB0; // A3
+    adc2.set_resolution(adc::Resolution::BITS14);
+    adc2.set_averaging(adc::Averaging::Samples1024);
+    adc2.set_sample_time(adc::SampleTime::CYCLES160_5);
+    let max2 = adc::resolution_to_max_count(adc::Resolution::BITS14);
+
+    // **** ADC4 init ****
+    let mut adc4 = adc4::Adc4::new(p.ADC4);
+    let mut adc4_pin1 = p.PC1; // A4
+    let mut adc4_pin2 = p.PC0; // A5
+    adc4.set_resolution(adc4::Resolution::BITS12);
+    adc4.set_averaging(adc4::Averaging::Samples256);
+    adc4.set_sample_time(adc4::SampleTime::CYCLES1_5);
+    let max4 = adc4::resolution_to_max_count(adc4::Resolution::BITS12);
+
+    // **** ADC1 blocking read ****
+    let raw: u16 = adc1.blocking_read(&mut adc1_pin1);
+    let volt: f32 = 3.3 * raw as f32 / max1 as f32;
+    info!("Read adc1 pin 1 {}", volt);
+
+    let raw: u16 = adc1.blocking_read(&mut adc1_pin2);
+    let volt: f32 = 3.3 * raw as f32 / max1 as f32;
+    info!("Read adc1 pin 2 {}", volt);
+
+    // **** ADC2 blocking read ****
+    let raw: u16 = adc2.blocking_read(&mut adc2_pin1);
+    let volt: f32 = 3.3 * raw as f32 / max2 as f32;
+    info!("Read adc2 pin 1 {}", volt);
+
+    let raw: u16 = adc2.blocking_read(&mut adc2_pin2);
+    let volt: f32 = 3.3 * raw as f32 / max2 as f32;
+    info!("Read adc2 pin 2 {}", volt);
+
+    // **** ADC4 blocking read ****
+    let raw: u16 = adc4.blocking_read(&mut adc4_pin1);
+    let volt: f32 = 3.3 * raw as f32 / max4 as f32;
+    info!("Read adc4 pin 1 {}", volt);
+
+    let raw: u16 = adc4.blocking_read(&mut adc4_pin2);
+    let volt: f32 = 3.3 * raw as f32 / max4 as f32;
+    info!("Read adc4 pin 2 {}", volt);
+
+    // **** ADC1 async read ****
+    let mut degraded11 = adc1_pin1.degrade_adc();
+    let mut degraded12 = adc1_pin2.degrade_adc();
+    let mut measurements = [0u16; 2];
+
+    adc1.read(
+        &mut p.GPDMA1_CH0,
+        [
+            (&mut degraded11, adc::SampleTime::CYCLES160_5),
+            (&mut degraded12, adc::SampleTime::CYCLES160_5),
+        ]
+        .into_iter(),
+        &mut measurements,
+    )
+    .await;
+    let volt1: f32 = 3.3 * measurements[0] as f32 / max1 as f32;
+    let volt2: f32 = 3.3 * measurements[1] as f32 / max1 as f32;
+
+    info!("Async read 1 pin 1 {}", volt1);
+    info!("Async read 1 pin 2 {}", volt2);
+
+    // **** ADC2 does not support async read ****
+
+    // **** ADC4 async read ****
+    let mut degraded41 = adc4_pin1.degrade_adc();
+    let mut degraded42 = adc4_pin2.degrade_adc();
+    let mut measurements = [0u16; 2];
+
+    // The channels must be in ascending order and can't repeat for ADC4
+    adc4.read(
+        &mut p.GPDMA1_CH1,
+        [&mut degraded42, &mut degraded41].into_iter(),
+        &mut measurements,
+    )
+    .await
+    .unwrap();
+    let volt2: f32 = 3.3 * measurements[0] as f32 / max4 as f32;
+    let volt1: f32 = 3.3 * measurements[1] as f32 / max4 as f32;
+    info!("Async read 4 pin 1 {}", volt1);
+    info!("Async read 4 pin 2 {}", volt2);
+}