diff options
| author | Priit Laes <[email protected]> | 2024-02-17 12:52:20 +0200 |
|---|---|---|
| committer | Priit Laes <[email protected]> | 2024-02-17 13:30:19 +0200 |
| commit | 1aa999c2a825bdaf6fa4c980f47428d9b1d9263f (patch) | |
| tree | 83941a63bf3b5e444f0efe50bb3888f5c0e2fff1 | |
| parent | 377e58e408f830f79171a470ba602b7d8bc525e4 (diff) | |
nrf: Use .is_empty() instead of .len() == 0
| -rw-r--r-- | embassy-nrf/src/pdm.rs | 2 | ||||
| -rwxr-xr-x | embassy-nrf/src/qspi.rs | 8 | ||||
| -rw-r--r-- | embassy-nrf/src/rng.rs | 2 | ||||
| -rw-r--r-- | embassy-nrf/src/twim.rs | 6 | ||||
| -rw-r--r-- | embassy-nrf/src/uarte.rs | 10 |
5 files changed, 14 insertions, 14 deletions
diff --git a/embassy-nrf/src/pdm.rs b/embassy-nrf/src/pdm.rs index 6ddc4dc0a..754d38310 100644 --- a/embassy-nrf/src/pdm.rs +++ b/embassy-nrf/src/pdm.rs | |||
| @@ -185,7 +185,7 @@ impl<'d, T: Instance> Pdm<'d, T> { | |||
| 185 | 185 | ||
| 186 | /// Sample data into the given buffer | 186 | /// Sample data into the given buffer |
| 187 | pub async fn sample(&mut self, buffer: &mut [i16]) -> Result<(), Error> { | 187 | pub async fn sample(&mut self, buffer: &mut [i16]) -> Result<(), Error> { |
| 188 | if buffer.len() == 0 { | 188 | if buffer.is_empty() { |
| 189 | return Err(Error::BufferZeroLength); | 189 | return Err(Error::BufferZeroLength); |
| 190 | } | 190 | } |
| 191 | if buffer.len() > EASY_DMA_SIZE { | 191 | if buffer.len() > EASY_DMA_SIZE { |
diff --git a/embassy-nrf/src/qspi.rs b/embassy-nrf/src/qspi.rs index 8eec09c96..4134a4c87 100755 --- a/embassy-nrf/src/qspi.rs +++ b/embassy-nrf/src/qspi.rs | |||
| @@ -402,7 +402,7 @@ impl<'d, T: Instance> Qspi<'d, T> { | |||
| 402 | /// a raw bus, not with flash memory. | 402 | /// a raw bus, not with flash memory. |
| 403 | pub async fn read_raw(&mut self, address: u32, data: &mut [u8]) -> Result<(), Error> { | 403 | pub async fn read_raw(&mut self, address: u32, data: &mut [u8]) -> Result<(), Error> { |
| 404 | // Avoid blocking_wait_ready() blocking forever on zero-length buffers. | 404 | // Avoid blocking_wait_ready() blocking forever on zero-length buffers. |
| 405 | if data.len() == 0 { | 405 | if data.is_empty() { |
| 406 | return Ok(()); | 406 | return Ok(()); |
| 407 | } | 407 | } |
| 408 | 408 | ||
| @@ -423,7 +423,7 @@ impl<'d, T: Instance> Qspi<'d, T> { | |||
| 423 | /// a raw bus, not with flash memory. | 423 | /// a raw bus, not with flash memory. |
| 424 | pub async fn write_raw(&mut self, address: u32, data: &[u8]) -> Result<(), Error> { | 424 | pub async fn write_raw(&mut self, address: u32, data: &[u8]) -> Result<(), Error> { |
| 425 | // Avoid blocking_wait_ready() blocking forever on zero-length buffers. | 425 | // Avoid blocking_wait_ready() blocking forever on zero-length buffers. |
| 426 | if data.len() == 0 { | 426 | if data.is_empty() { |
| 427 | return Ok(()); | 427 | return Ok(()); |
| 428 | } | 428 | } |
| 429 | 429 | ||
| @@ -444,7 +444,7 @@ impl<'d, T: Instance> Qspi<'d, T> { | |||
| 444 | /// a raw bus, not with flash memory. | 444 | /// a raw bus, not with flash memory. |
| 445 | pub fn blocking_read_raw(&mut self, address: u32, data: &mut [u8]) -> Result<(), Error> { | 445 | pub fn blocking_read_raw(&mut self, address: u32, data: &mut [u8]) -> Result<(), Error> { |
| 446 | // Avoid blocking_wait_ready() blocking forever on zero-length buffers. | 446 | // Avoid blocking_wait_ready() blocking forever on zero-length buffers. |
| 447 | if data.len() == 0 { | 447 | if data.is_empty() { |
| 448 | return Ok(()); | 448 | return Ok(()); |
| 449 | } | 449 | } |
| 450 | 450 | ||
| @@ -460,7 +460,7 @@ impl<'d, T: Instance> Qspi<'d, T> { | |||
| 460 | /// a raw bus, not with flash memory. | 460 | /// a raw bus, not with flash memory. |
| 461 | pub fn blocking_write_raw(&mut self, address: u32, data: &[u8]) -> Result<(), Error> { | 461 | pub fn blocking_write_raw(&mut self, address: u32, data: &[u8]) -> Result<(), Error> { |
| 462 | // Avoid blocking_wait_ready() blocking forever on zero-length buffers. | 462 | // Avoid blocking_wait_ready() blocking forever on zero-length buffers. |
| 463 | if data.len() == 0 { | 463 | if data.is_empty() { |
| 464 | return Ok(()); | 464 | return Ok(()); |
| 465 | } | 465 | } |
| 466 | 466 | ||
diff --git a/embassy-nrf/src/rng.rs b/embassy-nrf/src/rng.rs index 40b73231b..1c463fb7c 100644 --- a/embassy-nrf/src/rng.rs +++ b/embassy-nrf/src/rng.rs | |||
| @@ -108,7 +108,7 @@ impl<'d, T: Instance> Rng<'d, T> { | |||
| 108 | 108 | ||
| 109 | /// Fill the buffer with random bytes. | 109 | /// Fill the buffer with random bytes. |
| 110 | pub async fn fill_bytes(&mut self, dest: &mut [u8]) { | 110 | pub async fn fill_bytes(&mut self, dest: &mut [u8]) { |
| 111 | if dest.len() == 0 { | 111 | if dest.is_empty() { |
| 112 | return; // Nothing to fill | 112 | return; // Nothing to fill |
| 113 | } | 113 | } |
| 114 | 114 | ||
diff --git a/embassy-nrf/src/twim.rs b/embassy-nrf/src/twim.rs index da8e15d02..83971463f 100644 --- a/embassy-nrf/src/twim.rs +++ b/embassy-nrf/src/twim.rs | |||
| @@ -372,7 +372,7 @@ impl<'d, T: Instance> Twim<'d, T> { | |||
| 372 | // Start write operation. | 372 | // Start write operation. |
| 373 | r.shorts.write(|w| w.lasttx_stop().enabled()); | 373 | r.shorts.write(|w| w.lasttx_stop().enabled()); |
| 374 | r.tasks_starttx.write(|w| unsafe { w.bits(1) }); | 374 | r.tasks_starttx.write(|w| unsafe { w.bits(1) }); |
| 375 | if buffer.len() == 0 { | 375 | if buffer.is_empty() { |
| 376 | // With a zero-length buffer, LASTTX doesn't fire (because there's no last byte!), so do the STOP ourselves. | 376 | // With a zero-length buffer, LASTTX doesn't fire (because there's no last byte!), so do the STOP ourselves. |
| 377 | r.tasks_stop.write(|w| unsafe { w.bits(1) }); | 377 | r.tasks_stop.write(|w| unsafe { w.bits(1) }); |
| 378 | } | 378 | } |
| @@ -403,7 +403,7 @@ impl<'d, T: Instance> Twim<'d, T> { | |||
| 403 | // Start read operation. | 403 | // Start read operation. |
| 404 | r.shorts.write(|w| w.lastrx_stop().enabled()); | 404 | r.shorts.write(|w| w.lastrx_stop().enabled()); |
| 405 | r.tasks_startrx.write(|w| unsafe { w.bits(1) }); | 405 | r.tasks_startrx.write(|w| unsafe { w.bits(1) }); |
| 406 | if buffer.len() == 0 { | 406 | if buffer.is_empty() { |
| 407 | // With a zero-length buffer, LASTRX doesn't fire (because there's no last byte!), so do the STOP ourselves. | 407 | // With a zero-length buffer, LASTRX doesn't fire (because there's no last byte!), so do the STOP ourselves. |
| 408 | r.tasks_stop.write(|w| unsafe { w.bits(1) }); | 408 | r.tasks_stop.write(|w| unsafe { w.bits(1) }); |
| 409 | } | 409 | } |
| @@ -447,7 +447,7 @@ impl<'d, T: Instance> Twim<'d, T> { | |||
| 447 | w | 447 | w |
| 448 | }); | 448 | }); |
| 449 | r.tasks_starttx.write(|w| unsafe { w.bits(1) }); | 449 | r.tasks_starttx.write(|w| unsafe { w.bits(1) }); |
| 450 | if wr_buffer.len() == 0 && rd_buffer.len() == 0 { | 450 | if wr_buffer.is_empty() && rd_buffer.is_empty() { |
| 451 | // With a zero-length buffer, LASTRX/LASTTX doesn't fire (because there's no last byte!), so do the STOP ourselves. | 451 | // With a zero-length buffer, LASTRX/LASTTX doesn't fire (because there's no last byte!), so do the STOP ourselves. |
| 452 | // TODO handle when only one of the buffers is zero length | 452 | // TODO handle when only one of the buffers is zero length |
| 453 | r.tasks_stop.write(|w| unsafe { w.bits(1) }); | 453 | r.tasks_stop.write(|w| unsafe { w.bits(1) }); |
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs index de2966ba5..3d486452f 100644 --- a/embassy-nrf/src/uarte.rs +++ b/embassy-nrf/src/uarte.rs | |||
| @@ -386,7 +386,7 @@ impl<'d, T: Instance> UarteTx<'d, T> { | |||
| 386 | 386 | ||
| 387 | /// Same as [`write`](Self::write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more. | 387 | /// Same as [`write`](Self::write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more. |
| 388 | pub async fn write_from_ram(&mut self, buffer: &[u8]) -> Result<(), Error> { | 388 | pub async fn write_from_ram(&mut self, buffer: &[u8]) -> Result<(), Error> { |
| 389 | if buffer.len() == 0 { | 389 | if buffer.is_empty() { |
| 390 | return Ok(()); | 390 | return Ok(()); |
| 391 | } | 391 | } |
| 392 | 392 | ||
| @@ -456,7 +456,7 @@ impl<'d, T: Instance> UarteTx<'d, T> { | |||
| 456 | 456 | ||
| 457 | /// Same as [`write_from_ram`](Self::write_from_ram) but will fail instead of copying data into RAM. Consult the module level documentation to learn more. | 457 | /// Same as [`write_from_ram`](Self::write_from_ram) but will fail instead of copying data into RAM. Consult the module level documentation to learn more. |
| 458 | pub fn blocking_write_from_ram(&mut self, buffer: &[u8]) -> Result<(), Error> { | 458 | pub fn blocking_write_from_ram(&mut self, buffer: &[u8]) -> Result<(), Error> { |
| 459 | if buffer.len() == 0 { | 459 | if buffer.is_empty() { |
| 460 | return Ok(()); | 460 | return Ok(()); |
| 461 | } | 461 | } |
| 462 | 462 | ||
| @@ -694,7 +694,7 @@ impl<'d, T: Instance> UarteRx<'d, T> { | |||
| 694 | 694 | ||
| 695 | /// Read bytes until the buffer is filled. | 695 | /// Read bytes until the buffer is filled. |
| 696 | pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> { | 696 | pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> { |
| 697 | if buffer.len() == 0 { | 697 | if buffer.is_empty() { |
| 698 | return Ok(()); | 698 | return Ok(()); |
| 699 | } | 699 | } |
| 700 | if buffer.len() > EASY_DMA_SIZE { | 700 | if buffer.len() > EASY_DMA_SIZE { |
| @@ -775,7 +775,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> { | |||
| 775 | /// | 775 | /// |
| 776 | /// Returns the amount of bytes read. | 776 | /// Returns the amount of bytes read. |
| 777 | pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> { | 777 | pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> { |
| 778 | if buffer.len() == 0 { | 778 | if buffer.is_empty() { |
| 779 | return Ok(0); | 779 | return Ok(0); |
| 780 | } | 780 | } |
| 781 | if buffer.len() > EASY_DMA_SIZE { | 781 | if buffer.len() > EASY_DMA_SIZE { |
| @@ -848,7 +848,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> { | |||
| 848 | /// | 848 | /// |
| 849 | /// Returns the amount of bytes read. | 849 | /// Returns the amount of bytes read. |
| 850 | pub fn blocking_read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> { | 850 | pub fn blocking_read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> { |
| 851 | if buffer.len() == 0 { | 851 | if buffer.is_empty() { |
| 852 | return Ok(0); | 852 | return Ok(0); |
| 853 | } | 853 | } |
| 854 | if buffer.len() > EASY_DMA_SIZE { | 854 | if buffer.len() > EASY_DMA_SIZE { |
