rp/clocks: compactify pll setup

we don't need to preserve existing bits of the pll pwr register, so
let's only write and save a few instructions.

1 files changed, 7 insertions, 2 deletions

diff --git a/embassy-rp/src/clocks.rs b/embassy-rp/src/clocks.rs
index 9e581f105..cfc94f844 100644
--- a/embassy-rp/src/clocks.rs
+++ b/embassy-rp/src/clocks.rs
@@ -634,10 +634,12 @@ unsafe fn configure_pll(p: pac::pll::Pll, input_freq: u32, config: PllConfig) ->
     p.fbdiv_int().write(|w| w.set_fbdiv_int(config.fbdiv));
 
     // Turn on PLL
-    p.pwr().modify(|w| {
+    let pwr = p.pwr().write(|w| {
+        w.set_dsmpd(true); // "nothing is achieved by setting this low"
         w.set_pd(false);
         w.set_vcopd(false);
         w.set_postdivpd(true);
+        *w
     });
 
     // Wait for PLL to lock
@@ -650,7 +652,10 @@ unsafe fn configure_pll(p: pac::pll::Pll, input_freq: u32, config: PllConfig) ->
     });
 
     // Turn on post divider
-    p.pwr().modify(|w| w.set_postdivpd(false));
+    p.pwr().write(|w| {
+        *w = pwr;
+        w.set_postdivpd(false);
+    });
 
     vco_freq / ((config.post_div1 * config.post_div2) as u32)
 }