adc: fix start sequence for blocking_read

3 files changed, 23 insertions, 31 deletions

diff --git a/embassy-stm32/src/adc/adc4.rs b/embassy-stm32/src/adc/adc4.rs
index 472eb46fd..453513309 100644
--- a/embassy-stm32/src/adc/adc4.rs
+++ b/embassy-stm32/src/adc/adc4.rs
@@ -113,26 +113,11 @@ foreach_adc!(
             }
 
             fn enable() {
-                let cr_initial = ADC4::regs().cr().read();
-                let isr_initial = ADC4::regs().isr().read();
-
-                if cr_initial.aden() && isr_initial.adrdy() {
-                    return;
-                }
-
-                if cr_initial.aden() || cr_initial.adstart() {
-                    if cr_initial.adstart() {
-                        ADC4::regs().cr().modify(|w| w.set_adstp(true));
-                        while ADC4::regs().cr().read().adstart() {}
-                    }
-
-                    ADC4::regs().cr().modify(|w| w.set_addis(true));
-                    while ADC4::regs().cr().read().aden() {}
+                if !ADC4::regs().cr().read().aden()  || !ADC4::regs().isr().read().adrdy() {
+                    ADC4::regs().isr().write(|w| w.set_adrdy(true));
+                    ADC4::regs().cr().modify(|w| w.set_aden(true));
+                    while !ADC4::regs().isr().read().adrdy() {}
                 }
-
-                ADC4::regs().isr().write(|w| w.set_adrdy(true));
-                ADC4::regs().cr().modify(|w| w.set_aden(true));
-                while !ADC4::regs().isr().read().adrdy() {}
             }
 
             fn start() {
@@ -143,13 +128,17 @@ foreach_adc!(
             }
 
             fn stop() {
-                if ADC4::regs().cr().read().adstart() && !ADC4::regs().cr().read().addis() {
-                    ADC4::regs().cr().modify(|reg| {
-                        reg.set_adstp(true);
-                    });
+                let cr = ADC4::regs().cr().read();
+                if cr.adstart() {
+                    ADC4::regs().cr().modify(|w| w.set_adstp(true));
                     while ADC4::regs().cr().read().adstart() {}
                 }
 
+                if cr.aden() || cr.adstart() {
+                    ADC4::regs().cr().modify(|w| w.set_addis(true));
+                    while ADC4::regs().cr().read().aden() {}
+                }
+
                 // Reset configuration.
                 ADC4::regs().cfgr1().modify(|reg| {
                     reg.set_dmaen(false);
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 755cb78c2..6d53d9b91 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -192,6 +192,8 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
         #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
         channel.setup();
 
+        // Ensure no conversions are ongoing
+        T::stop();
         #[cfg(any(adc_v2, adc_v3, adc_g0, adc_h7rs, adc_u0, adc_u5, adc_wba, adc_c0))]
         T::enable();
         T::configure_sequence([((channel.channel(), channel.is_differential()), sample_time)].into_iter());
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index 341b15674..3c4431ae0 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -79,12 +79,17 @@ impl<T: Instance> super::SealedAnyInstance for T {
         T::regs().dr().as_ptr() as *mut u16
     }
 
-    fn enable() {}
+    fn enable() {
+        T::regs().cr2().modify(|reg| {
+            reg.set_adon(true);
+        });
+
+        blocking_delay_us(3);
+    }
 
     fn start() {
         // Begin ADC conversions
         T::regs().cr2().modify(|reg| {
-            reg.set_adon(true);
             reg.set_swstart(true);
         });
     }
@@ -198,7 +203,7 @@ impl<T: Instance> super::SealedAnyInstance for T {
 
 impl<'d, T> Adc<'d, T>
 where
-    T: Instance,
+    T: Instance + super::AnyInstance,
 {
     pub fn new(adc: Peri<'d, T>) -> Self {
         Self::new_with_config(adc, Default::default())
@@ -209,11 +214,7 @@ where
 
         let presc = from_pclk2(T::frequency());
         T::common_regs().ccr().modify(|w| w.set_adcpre(presc));
-        T::regs().cr2().modify(|reg| {
-            reg.set_adon(true);
-        });
-
-        blocking_delay_us(3);
+        T::enable();
 
         if let Some(resolution) = config.resolution {
             T::regs().cr1().modify(|reg| reg.set_res(resolution.into()));