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authorJuliDi <[email protected]>2023-06-19 13:46:17 +0200
committerJuliDi <[email protected]>2023-06-19 13:46:17 +0200
commit218b102b2840c9786944aa6f613450c876b6110b (patch)
treed411642bd7d3a75a9562219fd07a2dc38b124b85
parentfe7b72948ab5d3682f23e305f3eb7186cc308b1b (diff)
remove Alignment and make Value and Value array look the same
-rw-r--r--embassy-stm32/src/dac/mod.rs20
1 files changed, 10 insertions, 10 deletions
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 4384a7c34..0fbf67673 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -86,23 +86,23 @@ impl Ch2Trigger {
86 86
87#[derive(Debug, Copy, Clone, Eq, PartialEq)] 87#[derive(Debug, Copy, Clone, Eq, PartialEq)]
88#[cfg_attr(feature = "defmt", derive(defmt::Format))] 88#[cfg_attr(feature = "defmt", derive(defmt::Format))]
89pub enum Alignment {
90 Left,
91 Right,
92}
93
94#[derive(Debug, Copy, Clone, Eq, PartialEq)]
95#[cfg_attr(feature = "defmt", derive(defmt::Format))]
96pub enum Value { 89pub enum Value {
90 // 8 bit value
97 Bit8(u8), 91 Bit8(u8),
98 Bit12(u16, Alignment), 92 // 12 bit value stored in a u16, left-aligned
93 Bit12Left(u16),
94 // 12 bit value stored in a u16, right-aligned
95 Bit12Right(u16),
99} 96}
100 97
101#[derive(Debug, Copy, Clone, Eq, PartialEq)] 98#[derive(Debug, Copy, Clone, Eq, PartialEq)]
102#[cfg_attr(feature = "defmt", derive(defmt::Format))] 99#[cfg_attr(feature = "defmt", derive(defmt::Format))]
103pub enum ValueArray<'a> { 100pub enum ValueArray<'a> {
101 // 8 bit values
104 Bit8(&'a [u8]), 102 Bit8(&'a [u8]),
103 // 12 bit value stored in a u16, left-aligned
105 Bit12Left(&'a [u16]), 104 Bit12Left(&'a [u16]),
105 // 12 bit values stored in a u16, right-aligned
106 Bit12Right(&'a [u16]), 106 Bit12Right(&'a [u16]),
107} 107}
108 108
@@ -225,8 +225,8 @@ impl<'d, T: Instance, Tx> Dac<'d, T, Tx> {
225 self.check_channel_exists(ch)?; 225 self.check_channel_exists(ch)?;
226 match value { 226 match value {
227 Value::Bit8(v) => T::regs().dhr8r(ch.index()).write(|reg| reg.set_dhr(v)), 227 Value::Bit8(v) => T::regs().dhr8r(ch.index()).write(|reg| reg.set_dhr(v)),
228 Value::Bit12(v, Alignment::Left) => T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v)), 228 Value::Bit12Left(v) => T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v)),
229 Value::Bit12(v, Alignment::Right) => T::regs().dhr12r(ch.index()).write(|reg| reg.set_dhr(v)), 229 Value::Bit12Right(v) => T::regs().dhr12r(ch.index()).write(|reg| reg.set_dhr(v)),
230 } 230 }
231 Ok(()) 231 Ok(())
232 } 232 }