diff options
| author | Bob McWhirter <[email protected]> | 2021-05-20 14:19:43 -0400 |
|---|---|---|
| committer | Bob McWhirter <[email protected]> | 2021-05-20 14:19:43 -0400 |
| commit | 222faccbab5d2b37c377885ab0c8aeb90e922d6d (patch) | |
| tree | 00dfc5d1b195e5bc630a8fff5204441ae96dae8c | |
| parent | 8b36269d65ecf7c0f314e5e30e0d8cf3abef338c (diff) | |
Formatting.
| -rw-r--r-- | embassy-stm32/src/spi/v1.rs | 30 | ||||
| -rw-r--r-- | embassy-stm32/src/spi/v2.rs | 30 | ||||
| -rw-r--r-- | embassy-stm32/src/spi/v3.rs | 51 |
3 files changed, 31 insertions, 80 deletions
diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs index fd0a0e7f3..95afaa673 100644 --- a/embassy-stm32/src/spi/v1.rs +++ b/embassy-stm32/src/spi/v1.rs | |||
| @@ -5,10 +5,10 @@ use crate::pac::spi; | |||
| 5 | use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; | 5 | use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; |
| 6 | use crate::time::Hertz; | 6 | use crate::time::Hertz; |
| 7 | use core::marker::PhantomData; | 7 | use core::marker::PhantomData; |
| 8 | use core::ptr; | ||
| 8 | use embassy::util::Unborrow; | 9 | use embassy::util::Unborrow; |
| 9 | use embassy_extras::unborrow; | 10 | use embassy_extras::unborrow; |
| 10 | pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; | 11 | pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; |
| 11 | use core::ptr; | ||
| 12 | 12 | ||
| 13 | impl WordSize { | 13 | impl WordSize { |
| 14 | fn dff(&self) -> spi::vals::Dff { | 14 | fn dff(&self) -> spi::vals::Dff { |
| @@ -153,10 +153,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> { | |||
| 153 | } | 153 | } |
| 154 | unsafe { | 154 | unsafe { |
| 155 | let dr = regs.txdr().ptr() as *mut u8; | 155 | let dr = regs.txdr().ptr() as *mut u8; |
| 156 | ptr::write_volatile( | 156 | ptr::write_volatile(dr, *word); |
| 157 | dr, | ||
| 158 | *word, | ||
| 159 | ); | ||
| 160 | } | 157 | } |
| 161 | loop { | 158 | loop { |
| 162 | let sr = unsafe { regs.sr().read() }; | 159 | let sr = unsafe { regs.sr().read() }; |
| @@ -192,10 +189,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> { | |||
| 192 | } | 189 | } |
| 193 | unsafe { | 190 | unsafe { |
| 194 | let dr = regs.txdr().ptr() as *mut u8; | 191 | let dr = regs.txdr().ptr() as *mut u8; |
| 195 | ptr::write_volatile( | 192 | ptr::write_volatile(dr, *word); |
| 196 | dr, | ||
| 197 | *word, | ||
| 198 | ); | ||
| 199 | } | 193 | } |
| 200 | 194 | ||
| 201 | while unsafe { !regs.sr().read().rxne() } { | 195 | while unsafe { !regs.sr().read().rxne() } { |
| @@ -204,9 +198,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> { | |||
| 204 | 198 | ||
| 205 | unsafe { | 199 | unsafe { |
| 206 | let dr = regs.dr().ptr() as *const u8; | 200 | let dr = regs.dr().ptr() as *const u8; |
| 207 | *word = ptr::read_volatile( | 201 | *word = ptr::read_volatile(dr); |
| 208 | dr | ||
| 209 | ); | ||
| 210 | } | 202 | } |
| 211 | 203 | ||
| 212 | let sr = unsafe { regs.sr().read() }; | 204 | let sr = unsafe { regs.sr().read() }; |
| @@ -238,10 +230,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> { | |||
| 238 | } | 230 | } |
| 239 | unsafe { | 231 | unsafe { |
| 240 | let dr = regs.txdr().ptr() as *mut u16; | 232 | let dr = regs.txdr().ptr() as *mut u16; |
| 241 | ptr::write_volatile( | 233 | ptr::write_volatile(dr, *word); |
| 242 | dr, | ||
| 243 | *word, | ||
| 244 | ); | ||
| 245 | } | 234 | } |
| 246 | loop { | 235 | loop { |
| 247 | let sr = unsafe { regs.sr().read() }; | 236 | let sr = unsafe { regs.sr().read() }; |
| @@ -277,19 +266,14 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T> | |||
| 277 | } | 266 | } |
| 278 | unsafe { | 267 | unsafe { |
| 279 | let dr = regs.txdr().ptr() as *mut u16; | 268 | let dr = regs.txdr().ptr() as *mut u16; |
| 280 | ptr::write_volatile( | 269 | ptr::write_volatile(dr, *word); |
| 281 | dr, | ||
| 282 | *word, | ||
| 283 | ); | ||
| 284 | } | 270 | } |
| 285 | while unsafe { !regs.sr().read().rxne() } { | 271 | while unsafe { !regs.sr().read().rxne() } { |
| 286 | // spin waiting for inbound to shift in. | 272 | // spin waiting for inbound to shift in. |
| 287 | } | 273 | } |
| 288 | unsafe { | 274 | unsafe { |
| 289 | let dr = regs.dr().ptr() as *const u16; | 275 | let dr = regs.dr().ptr() as *const u16; |
| 290 | *word = ptr::read_volatile( | 276 | *word = ptr::read_volatile(dr); |
| 291 | dr | ||
| 292 | ); | ||
| 293 | } | 277 | } |
| 294 | 278 | ||
| 295 | let sr = unsafe { regs.sr().read() }; | 279 | let sr = unsafe { regs.sr().read() }; |
diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs index 82344a5d6..00ea10820 100644 --- a/embassy-stm32/src/spi/v2.rs +++ b/embassy-stm32/src/spi/v2.rs | |||
| @@ -7,10 +7,10 @@ use crate::pac::spi; | |||
| 7 | use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; | 7 | use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; |
| 8 | use crate::time::Hertz; | 8 | use crate::time::Hertz; |
| 9 | use core::marker::PhantomData; | 9 | use core::marker::PhantomData; |
| 10 | use core::ptr; | ||
| 10 | use embassy::util::Unborrow; | 11 | use embassy::util::Unborrow; |
| 11 | use embassy_extras::unborrow; | 12 | use embassy_extras::unborrow; |
| 12 | pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; | 13 | pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; |
| 13 | use core::ptr; | ||
| 14 | 14 | ||
| 15 | impl WordSize { | 15 | impl WordSize { |
| 16 | fn ds(&self) -> spi::vals::Ds { | 16 | fn ds(&self) -> spi::vals::Ds { |
| @@ -166,10 +166,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> { | |||
| 166 | } | 166 | } |
| 167 | unsafe { | 167 | unsafe { |
| 168 | let dr = regs.dr().ptr() as *mut u8; | 168 | let dr = regs.dr().ptr() as *mut u8; |
| 169 | ptr::write_volatile( | 169 | ptr::write_volatile(dr, *word); |
| 170 | dr, | ||
| 171 | *word, | ||
| 172 | ); | ||
| 173 | } | 170 | } |
| 174 | loop { | 171 | loop { |
| 175 | let sr = unsafe { regs.sr().read() }; | 172 | let sr = unsafe { regs.sr().read() }; |
| @@ -205,10 +202,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> { | |||
| 205 | } | 202 | } |
| 206 | unsafe { | 203 | unsafe { |
| 207 | let dr = regs.dr().ptr() as *mut u8; | 204 | let dr = regs.dr().ptr() as *mut u8; |
| 208 | ptr::write_volatile( | 205 | ptr::write_volatile(dr, *word); |
| 209 | dr, | ||
| 210 | *word, | ||
| 211 | ); | ||
| 212 | } | 206 | } |
| 213 | loop { | 207 | loop { |
| 214 | let sr = unsafe { regs.sr().read() }; | 208 | let sr = unsafe { regs.sr().read() }; |
| @@ -227,9 +221,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> { | |||
| 227 | } | 221 | } |
| 228 | unsafe { | 222 | unsafe { |
| 229 | let dr = regs.rxdr().ptr() as *const u8; | 223 | let dr = regs.rxdr().ptr() as *const u8; |
| 230 | *word = ptr::read_volatile( | 224 | *word = ptr::read_volatile(dr); |
| 231 | dr | ||
| 232 | ); | ||
| 233 | } | 225 | } |
| 234 | let sr = unsafe { regs.sr().read() }; | 226 | let sr = unsafe { regs.sr().read() }; |
| 235 | if sr.fre() { | 227 | if sr.fre() { |
| @@ -260,10 +252,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> { | |||
| 260 | } | 252 | } |
| 261 | unsafe { | 253 | unsafe { |
| 262 | let dr = regs.dr().ptr() as *mut u16; | 254 | let dr = regs.dr().ptr() as *mut u16; |
| 263 | ptr::write_volatile( | 255 | ptr::write_volatile(dr, *word); |
| 264 | dr, | ||
| 265 | *word, | ||
| 266 | ); | ||
| 267 | } | 256 | } |
| 268 | loop { | 257 | loop { |
| 269 | let sr = unsafe { regs.sr().read() }; | 258 | let sr = unsafe { regs.sr().read() }; |
| @@ -299,19 +288,14 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T> | |||
| 299 | } | 288 | } |
| 300 | unsafe { | 289 | unsafe { |
| 301 | let dr = regs.dr().ptr() as *mut u16; | 290 | let dr = regs.dr().ptr() as *mut u16; |
| 302 | ptr::write_volatile( | 291 | ptr::write_volatile(dr, *word); |
| 303 | dr, | ||
| 304 | *word, | ||
| 305 | ); | ||
| 306 | } | 292 | } |
| 307 | while unsafe { !regs.sr().read().rxne() } { | 293 | while unsafe { !regs.sr().read().rxne() } { |
| 308 | // spin waiting for inbound to shift in. | 294 | // spin waiting for inbound to shift in. |
| 309 | } | 295 | } |
| 310 | unsafe { | 296 | unsafe { |
| 311 | let dr = regs.rxdr().ptr() as *const u16; | 297 | let dr = regs.rxdr().ptr() as *const u16; |
| 312 | *word = ptr::read_volatile( | 298 | *word = ptr::read_volatile(dr); |
| 313 | dr | ||
| 314 | ); | ||
| 315 | } | 299 | } |
| 316 | let sr = unsafe { regs.sr().read() }; | 300 | let sr = unsafe { regs.sr().read() }; |
| 317 | if sr.fre() { | 301 | if sr.fre() { |
diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs index e30d479ee..c3f66430c 100644 --- a/embassy-stm32/src/spi/v3.rs +++ b/embassy-stm32/src/spi/v3.rs | |||
| @@ -7,11 +7,10 @@ use crate::pac::spi; | |||
| 7 | use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; | 7 | use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; |
| 8 | use crate::time::Hertz; | 8 | use crate::time::Hertz; |
| 9 | use core::marker::PhantomData; | 9 | use core::marker::PhantomData; |
| 10 | use core::ptr; | ||
| 10 | use embassy::util::Unborrow; | 11 | use embassy::util::Unborrow; |
| 11 | use embassy_extras::unborrow; | 12 | use embassy_extras::unborrow; |
| 12 | pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; | 13 | pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; |
| 13 | use core::ptr; | ||
| 14 | |||
| 15 | 14 | ||
| 16 | impl WordSize { | 15 | impl WordSize { |
| 17 | fn dsize(&self) -> u8 { | 16 | fn dsize(&self) -> u8 { |
| @@ -40,15 +39,15 @@ pub struct Spi<'d, T: Instance> { | |||
| 40 | impl<'d, T: Instance> Spi<'d, T> { | 39 | impl<'d, T: Instance> Spi<'d, T> { |
| 41 | pub fn new<F>( | 40 | pub fn new<F>( |
| 42 | pclk: Hertz, | 41 | pclk: Hertz, |
| 43 | peri: impl Unborrow<Target=T> + 'd, | 42 | peri: impl Unborrow<Target = T> + 'd, |
| 44 | sck: impl Unborrow<Target=impl SckPin<T>>, | 43 | sck: impl Unborrow<Target = impl SckPin<T>>, |
| 45 | mosi: impl Unborrow<Target=impl MosiPin<T>>, | 44 | mosi: impl Unborrow<Target = impl MosiPin<T>>, |
| 46 | miso: impl Unborrow<Target=impl MisoPin<T>>, | 45 | miso: impl Unborrow<Target = impl MisoPin<T>>, |
| 47 | freq: F, | 46 | freq: F, |
| 48 | config: Config, | 47 | config: Config, |
| 49 | ) -> Self | 48 | ) -> Self |
| 50 | where | 49 | where |
| 51 | F: Into<Hertz>, | 50 | F: Into<Hertz>, |
| 52 | { | 51 | { |
| 53 | unborrow!(peri); | 52 | unborrow!(peri); |
| 54 | unborrow!(sck, mosi, miso); | 53 | unborrow!(sck, mosi, miso); |
| @@ -67,9 +66,7 @@ impl<'d, T: Instance> Spi<'d, T> { | |||
| 67 | 66 | ||
| 68 | let br = Self::compute_baud_rate(pclk, freq.into()); | 67 | let br = Self::compute_baud_rate(pclk, freq.into()); |
| 69 | unsafe { | 68 | unsafe { |
| 70 | T::regs().ifcr().write(|w| { | 69 | T::regs().ifcr().write(|w| w.0 = 0xffff_ffff); |
| 71 | w.0 = 0xffff_ffff | ||
| 72 | }); | ||
| 73 | T::regs().cfg2().modify(|w| { | 70 | T::regs().cfg2().modify(|w| { |
| 74 | //w.set_ssoe(true); | 71 | //w.set_ssoe(true); |
| 75 | w.set_ssoe(false); | 72 | w.set_ssoe(false); |
| @@ -125,7 +122,9 @@ impl<'d, T: Instance> Spi<'d, T> { | |||
| 125 | let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) }; | 122 | let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) }; |
| 126 | block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE)); | 123 | block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE)); |
| 127 | block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num))); | 124 | block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num))); |
| 128 | block.ospeedr().modify(|w| w.set_ospeedr(pin, crate::pac::gpio::vals::Ospeedr::VERYHIGHSPEED)); | 125 | block |
| 126 | .ospeedr() | ||
| 127 | .modify(|w| w.set_ospeedr(pin, crate::pac::gpio::vals::Ospeedr::VERYHIGHSPEED)); | ||
| 129 | } | 128 | } |
| 130 | 129 | ||
| 131 | unsafe fn unconfigure_pin(block: Gpio, pin: usize) { | 130 | unsafe fn unconfigure_pin(block: Gpio, pin: usize) { |
| @@ -188,10 +187,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> { | |||
| 188 | } | 187 | } |
| 189 | unsafe { | 188 | unsafe { |
| 190 | let txdr = regs.txdr().ptr() as *mut u8; | 189 | let txdr = regs.txdr().ptr() as *mut u8; |
| 191 | ptr::write_volatile( | 190 | ptr::write_volatile(txdr, *word); |
| 192 | txdr, | ||
| 193 | *word, | ||
| 194 | ); | ||
| 195 | regs.cr1().modify(|reg| reg.set_cstart(true)); | 191 | regs.cr1().modify(|reg| reg.set_cstart(true)); |
| 196 | } | 192 | } |
| 197 | loop { | 193 | loop { |
| @@ -233,10 +229,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> { | |||
| 233 | } | 229 | } |
| 234 | unsafe { | 230 | unsafe { |
| 235 | let txdr = regs.txdr().ptr() as *mut u8; | 231 | let txdr = regs.txdr().ptr() as *mut u8; |
| 236 | ptr::write_volatile( | 232 | ptr::write_volatile(txdr, *word); |
| 237 | txdr, | ||
| 238 | *word, | ||
| 239 | ); | ||
| 240 | regs.cr1().modify(|reg| reg.set_cstart(true)); | 233 | regs.cr1().modify(|reg| reg.set_cstart(true)); |
| 241 | } | 234 | } |
| 242 | loop { | 235 | loop { |
| @@ -257,9 +250,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> { | |||
| 257 | } | 250 | } |
| 258 | unsafe { | 251 | unsafe { |
| 259 | let rxdr = regs.rxdr().ptr() as *const u8; | 252 | let rxdr = regs.rxdr().ptr() as *const u8; |
| 260 | *word = ptr::read_volatile( | 253 | *word = ptr::read_volatile(rxdr); |
| 261 | rxdr | ||
| 262 | ); | ||
| 263 | } | 254 | } |
| 264 | let sr = unsafe { regs.sr().read() }; | 255 | let sr = unsafe { regs.sr().read() }; |
| 265 | if sr.tifre() { | 256 | if sr.tifre() { |
| @@ -290,10 +281,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> { | |||
| 290 | } | 281 | } |
| 291 | unsafe { | 282 | unsafe { |
| 292 | let txdr = regs.txdr().ptr() as *mut u16; | 283 | let txdr = regs.txdr().ptr() as *mut u16; |
| 293 | ptr::write_volatile( | 284 | ptr::write_volatile(txdr, *word); |
| 294 | txdr, | ||
| 295 | *word, | ||
| 296 | ); | ||
| 297 | regs.cr1().modify(|reg| reg.set_cstart(true)); | 285 | regs.cr1().modify(|reg| reg.set_cstart(true)); |
| 298 | } | 286 | } |
| 299 | loop { | 287 | loop { |
| @@ -330,10 +318,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T> | |||
| 330 | } | 318 | } |
| 331 | unsafe { | 319 | unsafe { |
| 332 | let txdr = regs.txdr().ptr() as *mut u16; | 320 | let txdr = regs.txdr().ptr() as *mut u16; |
| 333 | ptr::write_volatile( | 321 | ptr::write_volatile(txdr, *word); |
| 334 | txdr, | ||
| 335 | *word, | ||
| 336 | ); | ||
| 337 | regs.cr1().modify(|reg| reg.set_cstart(true)); | 322 | regs.cr1().modify(|reg| reg.set_cstart(true)); |
| 338 | } | 323 | } |
| 339 | 324 | ||
| @@ -356,9 +341,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T> | |||
| 356 | 341 | ||
| 357 | unsafe { | 342 | unsafe { |
| 358 | let rxdr = regs.rxdr().ptr() as *const u16; | 343 | let rxdr = regs.rxdr().ptr() as *const u16; |
| 359 | *word = ptr::read_volatile( | 344 | *word = ptr::read_volatile(rxdr); |
| 360 | rxdr | ||
| 361 | ); | ||
| 362 | } | 345 | } |
| 363 | let sr = unsafe { regs.sr().read() }; | 346 | let sr = unsafe { regs.sr().read() }; |
| 364 | if sr.tifre() { | 347 | if sr.tifre() { |
