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authorDario Nieuwenhuis <[email protected]>2023-11-13 01:53:27 +0100
committerDario Nieuwenhuis <[email protected]>2023-11-13 01:56:50 +0100
commit2376b3bdfa573027c1ee4d66f8fdd6ca422a0fdd (patch)
tree7f5159472bc75c53734dc2559ab9b0579a28af79
parentf00e97a5f14b25d261eafba7cbc63b035c938996 (diff)
stm32/rcc: fix pll enum naming on f4, f7.
Diffstat
-rw-r--r--embassy-stm32/src/rcc/f4f7.rs10
-rw-r--r--examples/stm32f4/src/bin/eth.rs2
-rw-r--r--examples/stm32f4/src/bin/sdmmc.rs4
-rw-r--r--examples/stm32f4/src/bin/usb_ethernet.rs4
-rw-r--r--examples/stm32f4/src/bin/usb_raw.rs4
-rw-r--r--examples/stm32f4/src/bin/usb_serial.rs4
-rw-r--r--examples/stm32f7/src/bin/eth.rs2
-rw-r--r--examples/stm32f7/src/bin/sdmmc.rs4
-rw-r--r--examples/stm32f7/src/bin/usb_serial.rs4
-rw-r--r--tests/stm32/src/common.rs4
10 files changed, 21 insertions, 21 deletions
diff --git a/embassy-stm32/src/rcc/f4f7.rs b/embassy-stm32/src/rcc/f4f7.rs
index 9e8c639d0..718ba9b7c 100644
--- a/embassy-stm32/src/rcc/f4f7.rs
+++ b/embassy-stm32/src/rcc/f4f7.rs
@@ -1,7 +1,7 @@
1use crate::pac::pwr::vals::Vos; 1use crate::pac::pwr::vals::Vos;
2pub use crate::pac::rcc::vals::{ 2pub use crate::pac::rcc::vals::{
3 Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp, Pllq, Pllr, Pllsrc as PllSource, 3 Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv,
4 Ppre as APBPrescaler, Sw as Sysclk, 4 Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
5}; 5};
6use crate::pac::{FLASH, PWR, RCC}; 6use crate::pac::{FLASH, PWR, RCC};
7use crate::rcc::{set_freqs, Clocks}; 7use crate::rcc::{set_freqs, Clocks};
@@ -49,11 +49,11 @@ pub struct Pll {
49 pub mul: PllMul, 49 pub mul: PllMul,
50 50
51 /// PLL P division factor. If None, PLL P output is disabled. 51 /// PLL P division factor. If None, PLL P output is disabled.
52 pub divp: Option<Pllp>, 52 pub divp: Option<PllPDiv>,
53 /// PLL Q division factor. If None, PLL Q output is disabled. 53 /// PLL Q division factor. If None, PLL Q output is disabled.
54 pub divq: Option<Pllq>, 54 pub divq: Option<PllQDiv>,
55 /// PLL R division factor. If None, PLL R output is disabled. 55 /// PLL R division factor. If None, PLL R output is disabled.
56 pub divr: Option<Pllr>, 56 pub divr: Option<PllRDiv>,
57} 57}
58 58
59/// Configuration of the core clocks 59/// Configuration of the core clocks
diff --git a/examples/stm32f4/src/bin/eth.rs b/examples/stm32f4/src/bin/eth.rs
index 1747bbf4b..088d83c06 100644
--- a/examples/stm32f4/src/bin/eth.rs
+++ b/examples/stm32f4/src/bin/eth.rs
@@ -42,7 +42,7 @@ async fn main(spawner: Spawner) -> ! {
42 config.rcc.pll = Some(Pll { 42 config.rcc.pll = Some(Pll {
43 prediv: PllPreDiv::DIV4, 43 prediv: PllPreDiv::DIV4,
44 mul: PllMul::MUL180, 44 mul: PllMul::MUL180,
45 divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz. 45 divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
46 divq: None, 46 divq: None,
47 divr: None, 47 divr: None,
48 }); 48 });
diff --git a/examples/stm32f4/src/bin/sdmmc.rs b/examples/stm32f4/src/bin/sdmmc.rs
index 37e42384b..91747b2d5 100644
--- a/examples/stm32f4/src/bin/sdmmc.rs
+++ b/examples/stm32f4/src/bin/sdmmc.rs
@@ -30,8 +30,8 @@ async fn main(_spawner: Spawner) {
30 config.rcc.pll = Some(Pll { 30 config.rcc.pll = Some(Pll {
31 prediv: PllPreDiv::DIV4, 31 prediv: PllPreDiv::DIV4,
32 mul: PllMul::MUL168, 32 mul: PllMul::MUL168,
33 divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. 33 divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
34 divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. 34 divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
35 divr: None, 35 divr: None,
36 }); 36 });
37 config.rcc.ahb_pre = AHBPrescaler::DIV1; 37 config.rcc.ahb_pre = AHBPrescaler::DIV1;
diff --git a/examples/stm32f4/src/bin/usb_ethernet.rs b/examples/stm32f4/src/bin/usb_ethernet.rs
index 34407b95a..6bf5b1cba 100644
--- a/examples/stm32f4/src/bin/usb_ethernet.rs
+++ b/examples/stm32f4/src/bin/usb_ethernet.rs
@@ -56,8 +56,8 @@ async fn main(spawner: Spawner) {
56 config.rcc.pll = Some(Pll { 56 config.rcc.pll = Some(Pll {
57 prediv: PllPreDiv::DIV4, 57 prediv: PllPreDiv::DIV4,
58 mul: PllMul::MUL168, 58 mul: PllMul::MUL168,
59 divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. 59 divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
60 divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. 60 divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
61 divr: None, 61 divr: None,
62 }); 62 });
63 config.rcc.ahb_pre = AHBPrescaler::DIV1; 63 config.rcc.ahb_pre = AHBPrescaler::DIV1;
diff --git a/examples/stm32f4/src/bin/usb_raw.rs b/examples/stm32f4/src/bin/usb_raw.rs
index 689aea4fc..719b22bb9 100644
--- a/examples/stm32f4/src/bin/usb_raw.rs
+++ b/examples/stm32f4/src/bin/usb_raw.rs
@@ -85,8 +85,8 @@ async fn main(_spawner: Spawner) {
85 config.rcc.pll = Some(Pll { 85 config.rcc.pll = Some(Pll {
86 prediv: PllPreDiv::DIV4, 86 prediv: PllPreDiv::DIV4,
87 mul: PllMul::MUL168, 87 mul: PllMul::MUL168,
88 divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. 88 divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
89 divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. 89 divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
90 divr: None, 90 divr: None,
91 }); 91 });
92 config.rcc.ahb_pre = AHBPrescaler::DIV1; 92 config.rcc.ahb_pre = AHBPrescaler::DIV1;
diff --git a/examples/stm32f4/src/bin/usb_serial.rs b/examples/stm32f4/src/bin/usb_serial.rs
index 3e05b0ef2..e2ccc9142 100644
--- a/examples/stm32f4/src/bin/usb_serial.rs
+++ b/examples/stm32f4/src/bin/usb_serial.rs
@@ -32,8 +32,8 @@ async fn main(_spawner: Spawner) {
32 config.rcc.pll = Some(Pll { 32 config.rcc.pll = Some(Pll {
33 prediv: PllPreDiv::DIV4, 33 prediv: PllPreDiv::DIV4,
34 mul: PllMul::MUL168, 34 mul: PllMul::MUL168,
35 divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz. 35 divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
36 divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz. 36 divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
37 divr: None, 37 divr: None,
38 }); 38 });
39 config.rcc.ahb_pre = AHBPrescaler::DIV1; 39 config.rcc.ahb_pre = AHBPrescaler::DIV1;
diff --git a/examples/stm32f7/src/bin/eth.rs b/examples/stm32f7/src/bin/eth.rs
index 7c6c419a6..dd0069447 100644
--- a/examples/stm32f7/src/bin/eth.rs
+++ b/examples/stm32f7/src/bin/eth.rs
@@ -43,7 +43,7 @@ async fn main(spawner: Spawner) -> ! {
43 config.rcc.pll = Some(Pll { 43 config.rcc.pll = Some(Pll {
44 prediv: PllPreDiv::DIV4, 44 prediv: PllPreDiv::DIV4,
45 mul: PllMul::MUL216, 45 mul: PllMul::MUL216,
46 divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz 46 divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
47 divq: None, 47 divq: None,
48 divr: None, 48 divr: None,
49 }); 49 });
diff --git a/examples/stm32f7/src/bin/sdmmc.rs b/examples/stm32f7/src/bin/sdmmc.rs
index 430aa781f..990de0ab1 100644
--- a/examples/stm32f7/src/bin/sdmmc.rs
+++ b/examples/stm32f7/src/bin/sdmmc.rs
@@ -26,8 +26,8 @@ async fn main(_spawner: Spawner) {
26 config.rcc.pll = Some(Pll { 26 config.rcc.pll = Some(Pll {
27 prediv: PllPreDiv::DIV4, 27 prediv: PllPreDiv::DIV4,
28 mul: PllMul::MUL216, 28 mul: PllMul::MUL216,
29 divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz 29 divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
30 divq: Some(Pllq::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz 30 divq: Some(PllQDiv::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
31 divr: None, 31 divr: None,
32 }); 32 });
33 config.rcc.ahb_pre = AHBPrescaler::DIV1; 33 config.rcc.ahb_pre = AHBPrescaler::DIV1;
diff --git a/examples/stm32f7/src/bin/usb_serial.rs b/examples/stm32f7/src/bin/usb_serial.rs
index 6aca732b4..4991edbf0 100644
--- a/examples/stm32f7/src/bin/usb_serial.rs
+++ b/examples/stm32f7/src/bin/usb_serial.rs
@@ -32,8 +32,8 @@ async fn main(_spawner: Spawner) {
32 config.rcc.pll = Some(Pll { 32 config.rcc.pll = Some(Pll {
33 prediv: PllPreDiv::DIV4, 33 prediv: PllPreDiv::DIV4,
34 mul: PllMul::MUL216, 34 mul: PllMul::MUL216,
35 divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz 35 divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
36 divq: Some(Pllq::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz 36 divq: Some(PllQDiv::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
37 divr: None, 37 divr: None,
38 }); 38 });
39 config.rcc.ahb_pre = AHBPrescaler::DIV1; 39 config.rcc.ahb_pre = AHBPrescaler::DIV1;
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index e7367d5ed..fe694cbef 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -271,7 +271,7 @@ pub fn config() -> Config {
271 config.rcc.pll = Some(Pll { 271 config.rcc.pll = Some(Pll {
272 prediv: PllPreDiv::DIV4, 272 prediv: PllPreDiv::DIV4,
273 mul: PllMul::MUL180, 273 mul: PllMul::MUL180,
274 divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz. 274 divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
275 divq: None, 275 divq: None,
276 divr: None, 276 divr: None,
277 }); 277 });
@@ -292,7 +292,7 @@ pub fn config() -> Config {
292 config.rcc.pll = Some(Pll { 292 config.rcc.pll = Some(Pll {
293 prediv: PllPreDiv::DIV4, 293 prediv: PllPreDiv::DIV4,
294 mul: PllMul::MUL216, 294 mul: PllMul::MUL216,
295 divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz. 295 divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz.
296 divq: None, 296 divq: None,
297 divr: None, 297 divr: None,
298 }); 298 });
generated by cgit (git 2.34.1) at 2026-04-05 21:54:01 +0000