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authorIsmet Handzic <[email protected]>2024-04-06 11:33:58 -0400
committerDario Nieuwenhuis <[email protected]>2024-05-21 23:35:06 +0200
commit24032d0853adc799588dbc84315b3e72ec5bf7b2 (patch)
treecd28a3dbbf015d6740367276fa5d09cb27571fd5
parentc7c5723f8bacc10d54ee8f978f5ae99928e9881f (diff)
Remove generics from embassy-rp
-rw-r--r--embassy-rp/src/pwm.rs92
1 files changed, 50 insertions, 42 deletions
diff --git a/embassy-rp/src/pwm.rs b/embassy-rp/src/pwm.rs
index a1f400cfb..2e5aebc57 100644
--- a/embassy-rp/src/pwm.rs
+++ b/embassy-rp/src/pwm.rs
@@ -81,24 +81,22 @@ impl From<InputMode> for Divmode {
81} 81}
82 82
83/// PWM driver. 83/// PWM driver.
84pub struct Pwm<'d, T: Slice> { 84pub struct Pwm<'d> {
85 inner: PeripheralRef<'d, T>,
86 pin_a: Option<PeripheralRef<'d, AnyPin>>, 85 pin_a: Option<PeripheralRef<'d, AnyPin>>,
87 pin_b: Option<PeripheralRef<'d, AnyPin>>, 86 pin_b: Option<PeripheralRef<'d, AnyPin>>,
87 channel: usize,
88} 88}
89 89
90impl<'d, T: Slice> Pwm<'d, T> { 90impl<'d> Pwm<'d> {
91 fn new_inner( 91 fn new_inner(
92 inner: impl Peripheral<P = T> + 'd, 92 channel: usize,
93 a: Option<PeripheralRef<'d, AnyPin>>, 93 a: Option<PeripheralRef<'d, AnyPin>>,
94 b: Option<PeripheralRef<'d, AnyPin>>, 94 b: Option<PeripheralRef<'d, AnyPin>>,
95 b_pull: Pull, 95 b_pull: Pull,
96 config: Config, 96 config: Config,
97 divmode: Divmode, 97 divmode: Divmode,
98 ) -> Self { 98 ) -> Self {
99 into_ref!(inner); 99 let p = pac::PWM.ch(channel);
100
101 let p = inner.regs();
102 p.csr().modify(|w| { 100 p.csr().modify(|w| {
103 w.set_divmode(divmode); 101 w.set_divmode(divmode);
104 w.set_en(false); 102 w.set_en(false);
@@ -117,51 +115,66 @@ impl<'d, T: Slice> Pwm<'d, T> {
117 }); 115 });
118 } 116 }
119 Self { 117 Self {
120 inner, 118 // inner: p.into(),
121 pin_a: a, 119 pin_a: a,
122 pin_b: b, 120 pin_b: b,
121 channel,
123 } 122 }
124 } 123 }
125 124
126 /// Create PWM driver without any configured pins. 125 /// Create PWM driver without any configured pins.
127 #[inline] 126 #[inline]
128 pub fn new_free(inner: impl Peripheral<P = T> + 'd, config: Config) -> Self { 127 pub fn new_free<T: Slice>(channel: impl Peripheral<P = T> + 'd, config: Config) -> Self {
129 Self::new_inner(inner, None, None, Pull::None, config, Divmode::DIV) 128 Self::new_inner(channel.number(), None, None, Pull::None, config, Divmode::DIV)
130 } 129 }
131 130
132 /// Create PWM driver with a single 'a' as output. 131 /// Create PWM driver with a single 'a' as output.
133 #[inline] 132 #[inline]
134 pub fn new_output_a( 133 pub fn new_output_a<T: Slice>(
135 inner: impl Peripheral<P = T> + 'd, 134 channel: impl Peripheral<P = T> + 'd,
136 a: impl Peripheral<P = impl ChannelAPin<T>> + 'd, 135 a: impl Peripheral<P = impl ChannelAPin<T>> + 'd,
137 config: Config, 136 config: Config,
138 ) -> Self { 137 ) -> Self {
139 into_ref!(a); 138 into_ref!(a);
140 Self::new_inner(inner, Some(a.map_into()), None, Pull::None, config, Divmode::DIV) 139 Self::new_inner(
140 channel.number(),
141 Some(a.map_into()),
142 None,
143 Pull::None,
144 config,
145 Divmode::DIV,
146 )
141 } 147 }
142 148
143 /// Create PWM driver with a single 'b' pin as output. 149 /// Create PWM driver with a single 'b' pin as output.
144 #[inline] 150 #[inline]
145 pub fn new_output_b( 151 pub fn new_output_b<T: Slice>(
146 inner: impl Peripheral<P = T> + 'd, 152 channel: impl Peripheral<P = T> + 'd,
147 b: impl Peripheral<P = impl ChannelBPin<T>> + 'd, 153 b: impl Peripheral<P = impl ChannelBPin<T>> + 'd,
148 config: Config, 154 config: Config,
149 ) -> Self { 155 ) -> Self {
150 into_ref!(b); 156 into_ref!(b);
151 Self::new_inner(inner, None, Some(b.map_into()), Pull::None, config, Divmode::DIV) 157 Self::new_inner(
158 channel.number(),
159 None,
160 Some(b.map_into()),
161 Pull::None,
162 config,
163 Divmode::DIV,
164 )
152 } 165 }
153 166
154 /// Create PWM driver with a 'a' and 'b' pins as output. 167 /// Create PWM driver with a 'a' and 'b' pins as output.
155 #[inline] 168 #[inline]
156 pub fn new_output_ab( 169 pub fn new_output_ab<T: Slice>(
157 inner: impl Peripheral<P = T> + 'd, 170 channel: impl Peripheral<P = T> + 'd,
158 a: impl Peripheral<P = impl ChannelAPin<T>> + 'd, 171 a: impl Peripheral<P = impl ChannelAPin<T>> + 'd,
159 b: impl Peripheral<P = impl ChannelBPin<T>> + 'd, 172 b: impl Peripheral<P = impl ChannelBPin<T>> + 'd,
160 config: Config, 173 config: Config,
161 ) -> Self { 174 ) -> Self {
162 into_ref!(a, b); 175 into_ref!(a, b);
163 Self::new_inner( 176 Self::new_inner(
164 inner, 177 channel.number(),
165 Some(a.map_into()), 178 Some(a.map_into()),
166 Some(b.map_into()), 179 Some(b.map_into()),
167 Pull::None, 180 Pull::None,
@@ -172,21 +185,21 @@ impl<'d, T: Slice> Pwm<'d, T> {
172 185
173 /// Create PWM driver with a single 'b' as input pin. 186 /// Create PWM driver with a single 'b' as input pin.
174 #[inline] 187 #[inline]
175 pub fn new_input( 188 pub fn new_input<T: Slice>(
176 inner: impl Peripheral<P = T> + 'd, 189 channel: impl Peripheral<P = T> + 'd,
177 b: impl Peripheral<P = impl ChannelBPin<T>> + 'd, 190 b: impl Peripheral<P = impl ChannelBPin<T>> + 'd,
178 b_pull: Pull, 191 b_pull: Pull,
179 mode: InputMode, 192 mode: InputMode,
180 config: Config, 193 config: Config,
181 ) -> Self { 194 ) -> Self {
182 into_ref!(b); 195 into_ref!(b);
183 Self::new_inner(inner, None, Some(b.map_into()), b_pull, config, mode.into()) 196 Self::new_inner(channel.number(), None, Some(b.map_into()), b_pull, config, mode.into())
184 } 197 }
185 198
186 /// Create PWM driver with a 'a' and 'b' pins in the desired input mode. 199 /// Create PWM driver with a 'a' and 'b' pins in the desired input mode.
187 #[inline] 200 #[inline]
188 pub fn new_output_input( 201 pub fn new_output_input<T: Slice>(
189 inner: impl Peripheral<P = T> + 'd, 202 channel: impl Peripheral<P = T> + 'd,
190 a: impl Peripheral<P = impl ChannelAPin<T>> + 'd, 203 a: impl Peripheral<P = impl ChannelAPin<T>> + 'd,
191 b: impl Peripheral<P = impl ChannelBPin<T>> + 'd, 204 b: impl Peripheral<P = impl ChannelBPin<T>> + 'd,
192 b_pull: Pull, 205 b_pull: Pull,
@@ -195,7 +208,7 @@ impl<'d, T: Slice> Pwm<'d, T> {
195 ) -> Self { 208 ) -> Self {
196 into_ref!(a, b); 209 into_ref!(a, b);
197 Self::new_inner( 210 Self::new_inner(
198 inner, 211 channel.number(),
199 Some(a.map_into()), 212 Some(a.map_into()),
200 Some(b.map_into()), 213 Some(b.map_into()),
201 b_pull, 214 b_pull,
@@ -206,7 +219,7 @@ impl<'d, T: Slice> Pwm<'d, T> {
206 219
207 /// Set the PWM config. 220 /// Set the PWM config.
208 pub fn set_config(&mut self, config: &Config) { 221 pub fn set_config(&mut self, config: &Config) {
209 Self::configure(self.inner.regs(), config); 222 Self::configure(pac::PWM.ch(self.channel), config);
210 } 223 }
211 224
212 fn configure(p: pac::pwm::Channel, config: &Config) { 225 fn configure(p: pac::pwm::Channel, config: &Config) {
@@ -228,22 +241,22 @@ impl<'d, T: Slice> Pwm<'d, T> {
228 }); 241 });
229 } 242 }
230 243
231 /// Advances a slices output phase by one count while it is running 244 /// Advances a slice's output phase by one count while it is running
232 /// by inserting a pulse into the clock enable. The counter 245 /// by inserting a pulse into the clock enable. The counter
233 /// will not count faster than once per cycle. 246 /// will not count faster than once per cycle.
234 #[inline] 247 #[inline]
235 pub fn phase_advance(&mut self) { 248 pub fn phase_advance(&mut self) {
236 let p = self.inner.regs(); 249 let p = pac::PWM.ch(self.channel);
237 p.csr().write_set(|w| w.set_ph_adv(true)); 250 p.csr().write_set(|w| w.set_ph_adv(true));
238 while p.csr().read().ph_adv() {} 251 while p.csr().read().ph_adv() {}
239 } 252 }
240 253
241 /// Retards a slices output phase by one count while it is running 254 /// Retards a slice's output phase by one count while it is running
242 /// by deleting a pulse from the clock enable. The counter will not 255 /// by deleting a pulse from the clock enable. The counter will not
243 /// count backward when clock enable is permenantly low. 256 /// count backward when clock enable is permanently low.
244 #[inline] 257 #[inline]
245 pub fn phase_retard(&mut self) { 258 pub fn phase_retard(&mut self) {
246 let p = self.inner.regs(); 259 let p = pac::PWM.ch(self.channel);
247 p.csr().write_set(|w| w.set_ph_ret(true)); 260 p.csr().write_set(|w| w.set_ph_ret(true));
248 while p.csr().read().ph_ret() {} 261 while p.csr().read().ph_ret() {}
249 } 262 }
@@ -251,13 +264,13 @@ impl<'d, T: Slice> Pwm<'d, T> {
251 /// Read PWM counter. 264 /// Read PWM counter.
252 #[inline] 265 #[inline]
253 pub fn counter(&self) -> u16 { 266 pub fn counter(&self) -> u16 {
254 self.inner.regs().ctr().read().ctr() 267 pac::PWM.ch(self.channel).ctr().read().ctr()
255 } 268 }
256 269
257 /// Write PWM counter. 270 /// Write PWM counter.
258 #[inline] 271 #[inline]
259 pub fn set_counter(&self, ctr: u16) { 272 pub fn set_counter(&self, ctr: u16) {
260 self.inner.regs().ctr().write(|w| w.set_ctr(ctr)) 273 pac::PWM.ch(self.channel).ctr().write(|w| w.set_ctr(ctr))
261 } 274 }
262 275
263 /// Wait for channel interrupt. 276 /// Wait for channel interrupt.
@@ -281,7 +294,7 @@ impl<'d, T: Slice> Pwm<'d, T> {
281 294
282 #[inline] 295 #[inline]
283 fn bit(&self) -> u32 { 296 fn bit(&self) -> u32 {
284 1 << self.inner.number() as usize 297 1 << self.channel as usize
285 } 298 }
286} 299}
287 300
@@ -291,7 +304,7 @@ pub struct PwmBatch(u32);
291impl PwmBatch { 304impl PwmBatch {
292 #[inline] 305 #[inline]
293 /// Enable a PWM slice in this batch. 306 /// Enable a PWM slice in this batch.
294 pub fn enable(&mut self, pwm: &Pwm<'_, impl Slice>) { 307 pub fn enable(&mut self, pwm: &Pwm<'_>) {
295 self.0 |= pwm.bit(); 308 self.0 |= pwm.bit();
296 } 309 }
297 310
@@ -308,9 +321,9 @@ impl PwmBatch {
308 } 321 }
309} 322}
310 323
311impl<'d, T: Slice> Drop for Pwm<'d, T> { 324impl<'d> Drop for Pwm<'d> {
312 fn drop(&mut self) { 325 fn drop(&mut self) {
313 self.inner.regs().csr().write_clear(|w| w.set_en(false)); 326 pac::PWM.ch(self.channel).csr().write_clear(|w| w.set_en(false));
314 if let Some(pin) = &self.pin_a { 327 if let Some(pin) = &self.pin_a {
315 pin.gpio().ctrl().write(|w| w.set_funcsel(31)); 328 pin.gpio().ctrl().write(|w| w.set_funcsel(31));
316 } 329 }
@@ -327,11 +340,6 @@ trait SealedSlice {}
327pub trait Slice: Peripheral<P = Self> + SealedSlice + Sized + 'static { 340pub trait Slice: Peripheral<P = Self> + SealedSlice + Sized + 'static {
328 /// Slice number. 341 /// Slice number.
329 fn number(&self) -> u8; 342 fn number(&self) -> u8;
330
331 /// Slice register block.
332 fn regs(&self) -> pac::pwm::Channel {
333 pac::PWM.ch(self.number() as _)
334 }
335} 343}
336 344
337macro_rules! slice { 345macro_rules! slice {