diff options
| author | Andres Vahter <[email protected]> | 2023-10-24 10:11:54 +0300 |
|---|---|---|
| committer | Andres Vahter <[email protected]> | 2023-10-24 10:11:54 +0300 |
| commit | 25c2a9baaa863a42780e70791d6ab9df89f2dd3b (patch) | |
| tree | 403ae7ad420303129e1d98205ce4cb502f6c7ec1 | |
| parent | 1e362c750baca264e1ab199adb0f18f2098fa236 (diff) | |
stm32 uart: remove redundant set_fifoen(true)
| -rw-r--r-- | embassy-stm32/src/usart/buffered.rs | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs index 0e314c1d3..4daddfe91 100644 --- a/embassy-stm32/src/usart/buffered.rs +++ b/embassy-stm32/src/usart/buffered.rs | |||
| @@ -233,9 +233,6 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> { | |||
| 233 | configure(r, &config, T::frequency(), T::KIND, true, true)?; | 233 | configure(r, &config, T::frequency(), T::KIND, true, true)?; |
| 234 | 234 | ||
| 235 | r.cr1().modify(|w| { | 235 | r.cr1().modify(|w| { |
| 236 | #[cfg(usart_v4)] | ||
| 237 | w.set_fifoen(true); | ||
| 238 | |||
| 239 | w.set_rxneie(true); | 236 | w.set_rxneie(true); |
| 240 | w.set_idleie(true); | 237 | w.set_idleie(true); |
| 241 | }); | 238 | }); |
| @@ -257,9 +254,6 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> { | |||
| 257 | reconfigure::<T>(config)?; | 254 | reconfigure::<T>(config)?; |
| 258 | 255 | ||
| 259 | T::regs().cr1().modify(|w| { | 256 | T::regs().cr1().modify(|w| { |
| 260 | #[cfg(usart_v4)] | ||
| 261 | w.set_fifoen(true); | ||
| 262 | |||
| 263 | w.set_rxneie(true); | 257 | w.set_rxneie(true); |
| 264 | w.set_idleie(true); | 258 | w.set_idleie(true); |
| 265 | }); | 259 | }); |
| @@ -347,9 +341,6 @@ impl<'d, T: BasicInstance> BufferedUartRx<'d, T> { | |||
| 347 | reconfigure::<T>(config)?; | 341 | reconfigure::<T>(config)?; |
| 348 | 342 | ||
| 349 | T::regs().cr1().modify(|w| { | 343 | T::regs().cr1().modify(|w| { |
| 350 | #[cfg(usart_v4)] | ||
| 351 | w.set_fifoen(true); | ||
| 352 | |||
| 353 | w.set_rxneie(true); | 344 | w.set_rxneie(true); |
| 354 | w.set_idleie(true); | 345 | w.set_idleie(true); |
| 355 | }); | 346 | }); |
| @@ -431,9 +422,6 @@ impl<'d, T: BasicInstance> BufferedUartTx<'d, T> { | |||
| 431 | reconfigure::<T>(config)?; | 422 | reconfigure::<T>(config)?; |
| 432 | 423 | ||
| 433 | T::regs().cr1().modify(|w| { | 424 | T::regs().cr1().modify(|w| { |
| 434 | #[cfg(usart_v4)] | ||
| 435 | w.set_fifoen(true); | ||
| 436 | |||
| 437 | w.set_rxneie(true); | 425 | w.set_rxneie(true); |
| 438 | w.set_idleie(true); | 426 | w.set_idleie(true); |
| 439 | }); | 427 | }); |
