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authorThales Fragoso <[email protected]>2021-05-20 23:21:22 -0300
committerThales Fragoso <[email protected]>2021-05-21 20:20:17 -0300
commit2605dabca3996f3cff690eba121c9ef155014792 (patch)
tree06fef9701aae162f383615fd39b83667c3400b25
parentf5860c3c4c8b0d8a11cc73f42953047c7117fc93 (diff)
H7 RCC: Fix off by one error
-rw-r--r--embassy-stm32/src/rcc/h7/mod.rs3
1 files changed, 1 insertions, 2 deletions
diff --git a/embassy-stm32/src/rcc/h7/mod.rs b/embassy-stm32/src/rcc/h7/mod.rs
index 4f73835f9..d8d231bae 100644
--- a/embassy-stm32/src/rcc/h7/mod.rs
+++ b/embassy-stm32/src/rcc/h7/mod.rs
@@ -83,7 +83,6 @@ impl<'d> Rcc<'d> {
83 } 83 }
84 } 84 }
85 85
86 // TODO: FLASH and PWR
87 /// Freeze the core clocks, returning a Core Clocks Distribution 86 /// Freeze the core clocks, returning a Core Clocks Distribution
88 /// and Reset (CCDR) structure. The actual frequency of the clocks 87 /// and Reset (CCDR) structure. The actual frequency of the clocks
89 /// configured is returned in the `clocks` member of the CCDR 88 /// configured is returned in the `clocks` member of the CCDR
@@ -419,7 +418,7 @@ impl<'d> Rcc<'d> {
419 _ => (0b111, 16), 418 _ => (0b111, 16),
420 }; 419 };
421 let real_pclk = hclk / u32::from(ppre); 420 let real_pclk = hclk / u32::from(ppre);
422 assert!(real_pclk < max_pclk); 421 assert!(real_pclk <= max_pclk);
423 422
424 let tim_ker_clk = if let Some(tim_pre) = tim_pre { 423 let tim_ker_clk = if let Some(tim_pre) = tim_pre {
425 let clk = match (bits, tim_pre) { 424 let clk = match (bits, tim_pre) {