stm32: add async timeout functions to I2c and TimeoutI2c

2 files changed, 135 insertions, 9 deletions

diff --git a/embassy-stm32/src/i2c/timeout.rs b/embassy-stm32/src/i2c/timeout.rs
index bb6e105de..830de8e9a 100644
--- a/embassy-stm32/src/i2c/timeout.rs
+++ b/embassy-stm32/src/i2c/timeout.rs
@@ -27,6 +27,80 @@ impl<'a, 'd: 'a, T: Instance, TXDMA, RXDMA> TimeoutI2c<'a, 'd, T, TXDMA, RXDMA>
         Self { i2c, timeout }
     }
 
+    // =========================
+    //  Async public API
+
+    pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error>
+    where
+        TXDMA: crate::i2c::TxDma<T>,
+    {
+        self.write_timeout(address, write, self.timeout).await
+    }
+
+    pub async fn write_timeout(&mut self, address: u8, write: &[u8], timeout: Duration) -> Result<(), Error>
+    where
+        TXDMA: crate::i2c::TxDma<T>,
+    {
+        self.i2c.write_timeout(address, write, timeout_fn(timeout)).await
+    }
+
+    pub async fn write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error>
+    where
+        TXDMA: crate::i2c::TxDma<T>,
+    {
+        self.write_vectored_timeout(address, write, self.timeout).await
+    }
+
+    pub async fn write_vectored_timeout(&mut self, address: u8, write: &[&[u8]], timeout: Duration) -> Result<(), Error>
+    where
+        TXDMA: crate::i2c::TxDma<T>,
+    {
+        self.i2c
+            .write_vectored_timeout(address, write, timeout_fn(timeout))
+            .await
+    }
+
+    pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error>
+    where
+        RXDMA: crate::i2c::RxDma<T>,
+    {
+        self.read_timeout(address, buffer, self.timeout).await
+    }
+
+    pub async fn read_timeout(&mut self, address: u8, buffer: &mut [u8], timeout: Duration) -> Result<(), Error>
+    where
+        RXDMA: crate::i2c::RxDma<T>,
+    {
+        self.i2c.read_timeout(address, buffer, timeout_fn(timeout)).await
+    }
+
+    pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error>
+    where
+        TXDMA: super::TxDma<T>,
+        RXDMA: super::RxDma<T>,
+    {
+        self.write_read_timeout(address, write, read, self.timeout).await
+    }
+
+    pub async fn write_read_timeout(
+        &mut self,
+        address: u8,
+        write: &[u8],
+        read: &mut [u8],
+        timeout: Duration,
+    ) -> Result<(), Error>
+    where
+        TXDMA: super::TxDma<T>,
+        RXDMA: super::RxDma<T>,
+    {
+        self.i2c
+            .write_read_timeout(address, write, read, timeout_fn(timeout))
+            .await
+    }
+
+    // =========================
+    //  Blocking public API
+
     /// Blocking read with a custom timeout
     pub fn blocking_read_timeout(&mut self, addr: u8, read: &mut [u8], timeout: Duration) -> Result<(), Error> {
         self.i2c.blocking_read_timeout(addr, read, timeout_fn(timeout))
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index eaf980a4d..4327899bb 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -598,10 +598,22 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
     where
         TXDMA: crate::i2c::TxDma<T>,
     {
+        self.write_timeout(address, write, || Ok(())).await
+    }
+
+    pub async fn write_timeout(
+        &mut self,
+        address: u8,
+        write: &[u8],
+        check_timeout: impl Fn() -> Result<(), Error>,
+    ) -> Result<(), Error>
+    where
+        TXDMA: crate::i2c::TxDma<T>,
+    {
         if write.is_empty() {
-            self.write_internal(address, write, true, || Ok(()))
+            self.write_internal(address, write, true, check_timeout)
         } else {
-            self.write_dma_internal(address, write, true, true, || Ok(())).await
+            self.write_dma_internal(address, write, true, true, check_timeout).await
         }
     }
 
@@ -609,6 +621,18 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
     where
         TXDMA: crate::i2c::TxDma<T>,
     {
+        self.write_vectored_timeout(address, write, || Ok(())).await
+    }
+
+    pub async fn write_vectored_timeout(
+        &mut self,
+        address: u8,
+        write: &[&[u8]],
+        check_timeout: impl Fn() -> Result<(), Error>,
+    ) -> Result<(), Error>
+    where
+        TXDMA: crate::i2c::TxDma<T>,
+    {
         if write.is_empty() {
             return Err(Error::ZeroLengthTransfer);
         }
@@ -620,7 +644,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
             let next = iter.next();
             let is_last = next.is_none();
 
-            self.write_dma_internal(address, c, first, is_last, || Ok(())).await?;
+            self.write_dma_internal(address, c, first, is_last, || check_timeout())
+                .await?;
             first = false;
             current = next;
         }
@@ -631,10 +656,22 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
     where
         RXDMA: crate::i2c::RxDma<T>,
     {
+        self.read_timeout(address, buffer, || Ok(())).await
+    }
+
+    pub async fn read_timeout(
+        &mut self,
+        address: u8,
+        buffer: &mut [u8],
+        check_timeout: impl Fn() -> Result<(), Error>,
+    ) -> Result<(), Error>
+    where
+        RXDMA: crate::i2c::RxDma<T>,
+    {
         if buffer.is_empty() {
-            self.read_internal(address, buffer, false, || Ok(()))
+            self.read_internal(address, buffer, false, check_timeout)
         } else {
-            self.read_dma_internal(address, buffer, false, || Ok(())).await
+            self.read_dma_internal(address, buffer, false, check_timeout).await
         }
     }
 
@@ -643,16 +680,31 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
         TXDMA: super::TxDma<T>,
         RXDMA: super::RxDma<T>,
     {
+        self.write_read_timeout(address, write, read, || Ok(())).await
+    }
+
+    pub async fn write_read_timeout(
+        &mut self,
+        address: u8,
+        write: &[u8],
+        read: &mut [u8],
+        check_timeout: impl Fn() -> Result<(), Error>,
+    ) -> Result<(), Error>
+    where
+        TXDMA: super::TxDma<T>,
+        RXDMA: super::RxDma<T>,
+    {
         if write.is_empty() {
-            self.write_internal(address, write, false, || Ok(()))?;
+            self.write_internal(address, write, false, || check_timeout())?;
         } else {
-            self.write_dma_internal(address, write, true, true, || Ok(())).await?;
+            self.write_dma_internal(address, write, true, true, || check_timeout())
+                .await?;
         }
 
         if read.is_empty() {
-            self.read_internal(address, read, true, || Ok(()))?;
+            self.read_internal(address, read, true, check_timeout)?;
         } else {
-            self.read_dma_internal(address, read, true, || Ok(())).await?;
+            self.read_dma_internal(address, read, true, check_timeout).await?;
         }
 
         Ok(())