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authorROMemories <[email protected]>2025-05-21 11:36:55 +0200
committerROMemories <[email protected]>2025-05-21 14:19:09 +0200
commit26fb6eb9f65e7bf03302c26727ef7d6d940cf648 (patch)
treedf5f5c9484141d7e34418e380e3a9901e301a329
parent3fcfec7b943c3ac26668c1c168e549fe3009547e (diff)
feat(stm32-g0): provide a `const` constructor on `rcc::Config`
-rw-r--r--embassy-stm32/src/rcc/g0.rs17
1 files changed, 12 insertions, 5 deletions
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index e391b1210..c03cbf9a8 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -97,9 +97,9 @@ pub struct Config {
97 pub mux: super::mux::ClockMux, 97 pub mux: super::mux::ClockMux,
98} 98}
99 99
100impl Default for Config { 100impl Config {
101 #[inline] 101 #[inline]
102 fn default() -> Config { 102 pub const fn new() -> Self {
103 Config { 103 Config {
104 hsi: Some(Hsi { 104 hsi: Some(Hsi {
105 sys_div: HsiSysDiv::DIV1, 105 sys_div: HsiSysDiv::DIV1,
@@ -107,18 +107,25 @@ impl Default for Config {
107 hse: None, 107 hse: None,
108 sys: Sysclk::HSI, 108 sys: Sysclk::HSI,
109 #[cfg(crs)] 109 #[cfg(crs)]
110 hsi48: Some(Default::default()), 110 hsi48: Some(crate::rcc::Hsi48Config::new()),
111 pll: None, 111 pll: None,
112 ahb_pre: AHBPrescaler::DIV1, 112 ahb_pre: AHBPrescaler::DIV1,
113 apb1_pre: APBPrescaler::DIV1, 113 apb1_pre: APBPrescaler::DIV1,
114 low_power_run: false, 114 low_power_run: false,
115 ls: Default::default(), 115 ls: crate::rcc::LsConfig::new(),
116 voltage_range: VoltageRange::RANGE1, 116 voltage_range: VoltageRange::RANGE1,
117 mux: Default::default(), 117 mux: super::mux::ClockMux::default(),
118 } 118 }
119 } 119 }
120} 120}
121 121
122impl Default for Config {
123 #[inline]
124 fn default() -> Config {
125 Self::new()
126 }
127}
128
122#[derive(Default)] 129#[derive(Default)]
123pub struct PllFreq { 130pub struct PllFreq {
124 pub pll_p: Option<Hertz>, 131 pub pll_p: Option<Hertz>,