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authorbors[bot] <26634292+bors[bot]@users.noreply.github.com>2023-02-27 02:26:20 +0000
committerGitHub <[email protected]>2023-02-27 02:26:20 +0000
commit28b695e7c9b134cafcdfb5897d26b00e396c7776 (patch)
tree9daa6b70b5e1be84f6e9e1298429949dee50f126
parentbc71230cd07296468f2e03c00f9ceddbab67c9d9 (diff)
parent2331d58aa667d31ce74a2e10582a93b710c2aef7 (diff)
Merge #1243
1243: RP-PICO UART adding set_baudrate r=Dirbaio a=andres-hurtado-lopez The following PR attepts to bring fuctionality to allow change od UART baudrate changes during runtime. Changes where created under `@Dirbaio` supervision and discussed on issue: [https://github.com/embassy-rs/embassy/issues/1241#issuecomment-1445500175]( https://github.com/embassy-rs/embassy/issues/1241#issuecomment-1445500175) Co-authored-by: Andres Hurtado Lopez <[email protected]>
-rw-r--r--embassy-rp/src/uart/mod.rs49
1 files changed, 31 insertions, 18 deletions
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index bbbf97c01..42b3671a0 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -299,7 +299,7 @@ impl<'d, T: Instance> Uart<'d, T, Async> {
299 } 299 }
300} 300}
301 301
302impl<'d, T: Instance, M: Mode> Uart<'d, T, M> { 302impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
303 fn new_inner( 303 fn new_inner(
304 _uart: impl Peripheral<P = T> + 'd, 304 _uart: impl Peripheral<P = T> + 'd,
305 mut tx: PeripheralRef<'d, AnyPin>, 305 mut tx: PeripheralRef<'d, AnyPin>,
@@ -350,23 +350,7 @@ impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {
350 pin.pad_ctrl().write(|w| w.set_ie(true)); 350 pin.pad_ctrl().write(|w| w.set_ie(true));
351 } 351 }
352 352
353 let clk_base = crate::clocks::clk_peri_freq(); 353 Self::set_baudrate_inner(config.baudrate);
354
355 let baud_rate_div = (8 * clk_base) / config.baudrate;
356 let mut baud_ibrd = baud_rate_div >> 7;
357 let mut baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2;
358
359 if baud_ibrd == 0 {
360 baud_ibrd = 1;
361 baud_fbrd = 0;
362 } else if baud_ibrd >= 65535 {
363 baud_ibrd = 65535;
364 baud_fbrd = 0;
365 }
366
367 // Load PL011's baud divisor registers
368 r.uartibrd().write_value(pac::uart::regs::Uartibrd(baud_ibrd));
369 r.uartfbrd().write_value(pac::uart::regs::Uartfbrd(baud_fbrd));
370 354
371 let (pen, eps) = match config.parity { 355 let (pen, eps) = match config.parity {
372 Parity::ParityNone => (false, false), 356 Parity::ParityNone => (false, false),
@@ -400,6 +384,35 @@ impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {
400 }); 384 });
401 } 385 }
402 } 386 }
387
388 /// sets baudrate on runtime
389 pub fn set_baudrate(&mut self, baudrate: u32) {
390 Self::set_baudrate_inner(baudrate);
391 }
392
393 fn set_baudrate_inner(baudrate: u32) {
394 let r = T::regs();
395
396 let clk_base = crate::clocks::clk_peri_freq();
397
398 let baud_rate_div = (8 * clk_base) / baudrate;
399 let mut baud_ibrd = baud_rate_div >> 7;
400 let mut baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2;
401
402 if baud_ibrd == 0 {
403 baud_ibrd = 1;
404 baud_fbrd = 0;
405 } else if baud_ibrd >= 65535 {
406 baud_ibrd = 65535;
407 baud_fbrd = 0;
408 }
409
410 unsafe {
411 // Load PL011's baud divisor registers
412 r.uartibrd().write_value(pac::uart::regs::Uartibrd(baud_ibrd));
413 r.uartfbrd().write_value(pac::uart::regs::Uartfbrd(baud_fbrd));
414 }
415 }
403} 416}
404 417
405impl<'d, T: Instance, M: Mode> Uart<'d, T, M> { 418impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {