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authorBob McWhirter <[email protected]>2021-06-29 12:55:15 -0400
committerBob McWhirter <[email protected]>2021-06-29 12:55:15 -0400
commit2a25de3d3e16ebf8f21323ce016fe2ecf4d21629 (patch)
treef89b79d68d0646b95e8fd83b2c8492ecc3380fa5
parent6b78d56cebb79f53aecde1d4911779da35eeb864 (diff)
Make the metapac gen enr/rst missing regs non-fatal to the build.
Should be solved in a separate effort.
-rw-r--r--stm32-metapac/gen/src/lib.rs6
1 files changed, 3 insertions, 3 deletions
diff --git a/stm32-metapac/gen/src/lib.rs b/stm32-metapac/gen/src/lib.rs
index 1f969b3cd..a552c8cea 100644
--- a/stm32-metapac/gen/src/lib.rs
+++ b/stm32-metapac/gen/src/lib.rs
@@ -431,13 +431,13 @@ pub fn gen(options: Options) {
431 ]); 431 ]);
432 } 432 }
433 (None, Some(_)) => { 433 (None, Some(_)) => {
434 panic!("Unable to find enable register for {}", name) 434 print!("Unable to find enable register for {}", name)
435 } 435 }
436 (Some(_), None) => { 436 (Some(_), None) => {
437 panic!("Unable to find reset register for {}", name) 437 print!("Unable to find reset register for {}", name)
438 } 438 }
439 (None, None) => { 439 (None, None) => {
440 panic!("Unable to find enable and reset register for {}", name) 440 print!("Unable to find enable and reset register for {}", name)
441 } 441 }
442 } 442 }
443 } 443 }