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authornikvoid <[email protected]>2025-01-22 13:43:45 +0200
committernikvoid <[email protected]>2025-01-22 13:43:45 +0200
commit2d7e0b6e0fe4ee6ee1a7a32401ae3eeea3b08301 (patch)
tree4427254f0b9ecd110692505571d2083d025e6849
parent5885369f47d1260e58656bfc13bebba6339cf6cc (diff)
use `Delay` from `embassy-time` to wait for PHY response
-rw-r--r--embassy-stm32/src/eth/generic_smi.rs14
1 files changed, 8 insertions, 6 deletions
diff --git a/embassy-stm32/src/eth/generic_smi.rs b/embassy-stm32/src/eth/generic_smi.rs
index 06d01124f..ef673a301 100644
--- a/embassy-stm32/src/eth/generic_smi.rs
+++ b/embassy-stm32/src/eth/generic_smi.rs
@@ -3,7 +3,7 @@
3use core::task::Context; 3use core::task::Context;
4 4
5#[cfg(feature = "time")] 5#[cfg(feature = "time")]
6use embassy_time::{Duration, Timer}; 6use embassy_time::{Duration, Timer, Delay};
7#[cfg(feature = "time")] 7#[cfg(feature = "time")]
8use futures_util::FutureExt; 8use futures_util::FutureExt;
9 9
@@ -52,7 +52,7 @@ pub struct GenericSMI {
52impl GenericSMI { 52impl GenericSMI {
53 /// Construct the PHY. It assumes the address `phy_addr` in the SMI communication 53 /// Construct the PHY. It assumes the address `phy_addr` in the SMI communication
54 /// 54 ///
55 /// Set `phy_addr` to `0xFF` for automatic detection 55 /// Set `phy_addr` to `0xFF` for automatic detection (only with `time` feature enabled)
56 pub fn new(phy_addr: u8) -> Self { 56 pub fn new(phy_addr: u8) -> Self {
57 Self { 57 Self {
58 phy_addr, 58 phy_addr,
@@ -65,6 +65,7 @@ impl GenericSMI {
65unsafe impl PHY for GenericSMI { 65unsafe impl PHY for GenericSMI {
66 fn phy_reset<S: StationManagement>(&mut self, sm: &mut S) { 66 fn phy_reset<S: StationManagement>(&mut self, sm: &mut S) {
67 // Detect SMI address 67 // Detect SMI address
68 #[cfg(feature = "time")]
68 if self.phy_addr == 0xFF { 69 if self.phy_addr == 0xFF {
69 for addr in 0..32 { 70 for addr in 0..32 {
70 sm.smi_write(addr, PHY_REG_BCR, PHY_REG_BCR_RESET); 71 sm.smi_write(addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
@@ -74,14 +75,15 @@ unsafe impl PHY for GenericSMI {
74 self.phy_addr = addr; 75 self.phy_addr = addr;
75 return; 76 return;
76 } 77 }
77 cortex_m::asm::delay(1000); 78 embedded_hal_1::delay::DelayNs::delay_us(&mut Delay, 1000);
79 cortex_m::asm::delay(1000000);
78 } 80 }
79 } 81 }
80 panic!("PHY did not respond"); 82 panic!("PHY did not respond");
81 } else {
82 sm.smi_write(self.phy_addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
83 while sm.smi_read(self.phy_addr, PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}
84 } 83 }
84
85 sm.smi_write(self.phy_addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
86 while sm.smi_read(self.phy_addr, PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}
85 } 87 }
86 88
87 fn phy_init<S: StationManagement>(&mut self, sm: &mut S) { 89 fn phy_init<S: StationManagement>(&mut self, sm: &mut S) {