diff options
| author | Zoey Riordan <[email protected]> | 2022-04-27 20:33:41 +0200 |
|---|---|---|
| committer | Zoey Riordan <[email protected]> | 2022-04-27 20:33:41 +0200 |
| commit | 2ebc1186e035ced62acf29f812776a6cb7389855 (patch) | |
| tree | d6e762c413790d92136caeed4c2e70285b7b0ee4 | |
| parent | 5b3aaaaa9c1ff3b35f28f7babc628950192ef850 (diff) | |
Add split method to UarteWithIdle
| -rw-r--r-- | embassy-nrf/src/uarte.rs | 69 |
1 files changed, 49 insertions, 20 deletions
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs index 4f1c3da1e..8970b8a1e 100644 --- a/embassy-nrf/src/uarte.rs +++ b/embassy-nrf/src/uarte.rs | |||
| @@ -554,10 +554,8 @@ pub(in crate) fn drop_tx_rx(r: &pac::uarte0::RegisterBlock, s: &sealed::State) { | |||
| 554 | /// Interface to an UARTE peripheral that uses an additional timer and two PPI channels, | 554 | /// Interface to an UARTE peripheral that uses an additional timer and two PPI channels, |
| 555 | /// allowing it to implement the ReadUntilIdle trait. | 555 | /// allowing it to implement the ReadUntilIdle trait. |
| 556 | pub struct UarteWithIdle<'d, U: Instance, T: TimerInstance> { | 556 | pub struct UarteWithIdle<'d, U: Instance, T: TimerInstance> { |
| 557 | uarte: Uarte<'d, U>, | 557 | tx: UarteTx<'d, U>, |
| 558 | timer: Timer<'d, T>, | 558 | rx: UarteRxWithIdle<'d, U, T>, |
| 559 | ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 2>, | ||
| 560 | _ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 1>, | ||
| 561 | } | 559 | } |
| 562 | 560 | ||
| 563 | impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> { | 561 | impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> { |
| @@ -628,7 +626,8 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> { | |||
| 628 | config: Config, | 626 | config: Config, |
| 629 | ) -> Self { | 627 | ) -> Self { |
| 630 | let baudrate = config.baudrate; | 628 | let baudrate = config.baudrate; |
| 631 | let uarte = Uarte::new_inner(uarte, irq, rxd, txd, cts, rts, config); | 629 | let (tx, rx) = Uarte::new_inner(uarte, irq, rxd, txd, cts, rts, config).split(); |
| 630 | |||
| 632 | let mut timer = Timer::new(timer); | 631 | let mut timer = Timer::new(timer); |
| 633 | 632 | ||
| 634 | unborrow!(ppi_ch1, ppi_ch2); | 633 | unborrow!(ppi_ch1, ppi_ch2); |
| @@ -664,29 +663,64 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> { | |||
| 664 | ppi_ch2.enable(); | 663 | ppi_ch2.enable(); |
| 665 | 664 | ||
| 666 | Self { | 665 | Self { |
| 667 | uarte, | 666 | tx, |
| 668 | timer, | 667 | rx: UarteRxWithIdle { |
| 669 | ppi_ch1: ppi_ch1, | 668 | rx, |
| 670 | _ppi_ch2: ppi_ch2, | 669 | timer, |
| 670 | ppi_ch1: ppi_ch1, | ||
| 671 | _ppi_ch2: ppi_ch2, | ||
| 672 | }, | ||
| 671 | } | 673 | } |
| 672 | } | 674 | } |
| 673 | 675 | ||
| 676 | /// Split the Uarte into a transmitter and receiver, which is | ||
| 677 | /// particuarly useful when having two tasks correlating to | ||
| 678 | /// transmitting and receiving. | ||
| 679 | pub fn split(self) -> (UarteTx<'d, U>, UarteRxWithIdle<'d, U, T>) { | ||
| 680 | (self.tx, self.rx) | ||
| 681 | } | ||
| 682 | |||
| 674 | pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> { | 683 | pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> { |
| 675 | self.ppi_ch1.disable(); | 684 | self.rx.read(buffer).await |
| 676 | self.uarte.read(buffer).await | ||
| 677 | } | 685 | } |
| 678 | 686 | ||
| 679 | pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> { | 687 | pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> { |
| 680 | self.uarte.write(buffer).await | 688 | self.tx.write(buffer).await |
| 681 | } | 689 | } |
| 682 | 690 | ||
| 683 | pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> { | 691 | pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> { |
| 684 | self.ppi_ch1.disable(); | 692 | self.rx.blocking_read(buffer) |
| 685 | self.uarte.blocking_read(buffer) | ||
| 686 | } | 693 | } |
| 687 | 694 | ||
| 688 | pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> { | 695 | pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> { |
| 689 | self.uarte.blocking_write(buffer) | 696 | self.tx.blocking_write(buffer) |
| 697 | } | ||
| 698 | |||
| 699 | pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> { | ||
| 700 | self.rx.read_until_idle(buffer).await | ||
| 701 | } | ||
| 702 | |||
| 703 | pub fn blocking_read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> { | ||
| 704 | self.rx.blocking_read_until_idle(buffer) | ||
| 705 | } | ||
| 706 | } | ||
| 707 | |||
| 708 | pub struct UarteRxWithIdle<'d, U: Instance, T: TimerInstance> { | ||
| 709 | rx: UarteRx<'d, U>, | ||
| 710 | timer: Timer<'d, T>, | ||
| 711 | ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 2>, | ||
| 712 | _ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 1>, | ||
| 713 | } | ||
| 714 | |||
| 715 | impl<'d, U: Instance, T: TimerInstance> UarteRxWithIdle<'d, U, T> { | ||
| 716 | pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> { | ||
| 717 | self.ppi_ch1.disable(); | ||
| 718 | self.rx.read(buffer).await | ||
| 719 | } | ||
| 720 | |||
| 721 | pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> { | ||
| 722 | self.ppi_ch1.disable(); | ||
| 723 | self.rx.blocking_read(buffer) | ||
| 690 | } | 724 | } |
| 691 | 725 | ||
| 692 | pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> { | 726 | pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> { |
| @@ -706,8 +740,6 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> { | |||
| 706 | self.ppi_ch1.enable(); | 740 | self.ppi_ch1.enable(); |
| 707 | 741 | ||
| 708 | let drop = OnDrop::new(|| { | 742 | let drop = OnDrop::new(|| { |
| 709 | trace!("read drop: stopping"); | ||
| 710 | |||
| 711 | self.timer.stop(); | 743 | self.timer.stop(); |
| 712 | 744 | ||
| 713 | r.intenclr.write(|w| w.endrx().clear()); | 745 | r.intenclr.write(|w| w.endrx().clear()); |
| @@ -715,8 +747,6 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> { | |||
| 715 | r.tasks_stoprx.write(|w| unsafe { w.bits(1) }); | 747 | r.tasks_stoprx.write(|w| unsafe { w.bits(1) }); |
| 716 | 748 | ||
| 717 | while r.events_endrx.read().bits() == 0 {} | 749 | while r.events_endrx.read().bits() == 0 {} |
| 718 | |||
| 719 | trace!("read drop: stopped"); | ||
| 720 | }); | 750 | }); |
| 721 | 751 | ||
| 722 | r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) }); | 752 | r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) }); |
| @@ -785,7 +815,6 @@ impl<'d, U: Instance, T: TimerInstance> UarteWithIdle<'d, U, T> { | |||
| 785 | Ok(n) | 815 | Ok(n) |
| 786 | } | 816 | } |
| 787 | } | 817 | } |
| 788 | |||
| 789 | pub(crate) mod sealed { | 818 | pub(crate) mod sealed { |
| 790 | use core::sync::atomic::AtomicU8; | 819 | use core::sync::atomic::AtomicU8; |
| 791 | 820 | ||
