diff options
| author | Barnaby Walters <[email protected]> | 2024-02-16 19:58:19 +0100 |
|---|---|---|
| committer | Barnaby Walters <[email protected]> | 2024-02-16 19:58:19 +0100 |
| commit | 32e4c93954abb3add1c9b2c8fff627c497d47258 (patch) | |
| tree | 191453cdc9f62dc261df4bda7c92625e58c5f8fb | |
| parent | 396041ad1a954a09bb2cf45ea685ca8a1bbd8623 (diff) | |
Removed dangling doc comments
| -rw-r--r-- | embassy-stm32/src/rcc/g4.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs index c9ac2bb0b..5ac933af4 100644 --- a/embassy-stm32/src/rcc/g4.rs +++ b/embassy-stm32/src/rcc/g4.rs | |||
| @@ -356,10 +356,10 @@ mod max { | |||
| 356 | /// External Clock ?-48MHz (RM0440 p280) | 356 | /// External Clock ?-48MHz (RM0440 p280) |
| 357 | pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000); | 357 | pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000); |
| 358 | 358 | ||
| 359 | /// SYSCLK ?-170MHz (RM0440 p282) | 359 | // SYSCLK ?-170MHz (RM0440 p282) |
| 360 | //pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000); | 360 | //pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000); |
| 361 | 361 | ||
| 362 | /// PLL Output frequency ?-170MHz (RM0440 p281) | 362 | // PLL Output frequency ?-170MHz (RM0440 p281) |
| 363 | //pub(crate) const PCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000); | 363 | //pub(crate) const PCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000); |
| 364 | 364 | ||
| 365 | // Left over from f.rs, remove if not necessary | 365 | // Left over from f.rs, remove if not necessary |