Merge branch 'main' into timer_update_management

8 files changed, 95 insertions, 119 deletions

diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index 71b8cdafa..ca8758a15 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -8,6 +8,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## Unreleased - ReleaseDate
 
 - fix: Avoid generating timer update events when updating the frequency ([#4890](https://github.com/embassy-rs/embassy/pull/4890))
+- chore: cleanup low-power add time
+- fix: Allow setting SAI peripheral `frame_length` to `256`
 - fix: flash erase on dual-bank STM32Gxxx
 - feat: Add support for STM32N657X0
 - feat: timer: Add 32-bit timer support to SimplePwm waveform_up method following waveform pattern ([#4717](https://github.com/embassy-rs/embassy/pull/4717))
diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index bd8ccbf17..4957123a1 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -1,14 +1,12 @@
 #[cfg(stm32g4)]
 use pac::adc::regs::Difsel as DifselReg;
 #[allow(unused)]
+#[cfg(stm32g4)]
+pub use pac::adc::vals::{Adcaldif, Adstp, Difsel, Dmacfg, Dmaen, Exten, Rovsm, Trovs};
+#[allow(unused)]
 #[cfg(stm32h7)]
 use pac::adc::vals::{Adcaldif, Difsel, Exten};
-#[allow(unused)]
-#[cfg(stm32g4)]
-pub use pac::adc::vals::{Adcaldif, Difsel, Exten, Rovsm, Trovs};
-pub use pac::adccommon::vals::Presc;
-pub use stm32_metapac::adc::vals::{Adstp, Dmacfg, Dmaen};
-pub use stm32_metapac::adccommon::vals::Dual;
+pub use pac::adccommon::vals::{Dual, Presc};
 
 use super::{
     Adc, AnyAdcChannel, ConversionMode, Instance, RegularConversionMode, Resolution, RxDma, SampleTime,
@@ -176,6 +174,8 @@ impl<T: Instance> super::SealedAnyInstance for T {
     }
 
     fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+        T::regs().cr().modify(|w| w.set_aden(false));
+
         // Set sequence length
         T::regs().sqr1().modify(|w| {
             w.set_l(sequence.len() as u8 - 1);
@@ -183,36 +183,34 @@ impl<T: Instance> super::SealedAnyInstance for T {
 
         #[cfg(stm32g4)]
         let mut difsel = DifselReg::default();
+        let mut smpr = T::regs().smpr().read();
+        let mut smpr2 = T::regs().smpr2().read();
+        let mut sqr1 = T::regs().sqr1().read();
+        let mut sqr2 = T::regs().sqr2().read();
+        let mut sqr3 = T::regs().sqr3().read();
+        let mut sqr4 = T::regs().sqr4().read();
 
         // Configure channels and ranks
         for (_i, ((ch, is_differential), sample_time)) in sequence.enumerate() {
             let sample_time = sample_time.into();
             if ch <= 9 {
-                T::regs().smpr().modify(|reg| reg.set_smp(ch as _, sample_time));
+                smpr.set_smp(ch as _, sample_time);
             } else {
-                T::regs().smpr2().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
+                smpr2.set_smp((ch - 10) as _, sample_time);
             }
 
             match _i {
                 0..=3 => {
-                    T::regs().sqr1().modify(|w| {
-                        w.set_sq(_i, ch);
-                    });
+                    sqr1.set_sq(_i, ch);
                 }
                 4..=8 => {
-                    T::regs().sqr2().modify(|w| {
-                        w.set_sq(_i - 4, ch);
-                    });
+                    sqr2.set_sq(_i - 4, ch);
                 }
                 9..=13 => {
-                    T::regs().sqr3().modify(|w| {
-                        w.set_sq(_i - 9, ch);
-                    });
+                    sqr3.set_sq(_i - 9, ch);
                 }
                 14..=15 => {
-                    T::regs().sqr4().modify(|w| {
-                        w.set_sq(_i - 14, ch);
-                    });
+                    sqr4.set_sq(_i - 14, ch);
                 }
                 _ => unreachable!(),
             }
@@ -232,12 +230,14 @@ impl<T: Instance> super::SealedAnyInstance for T {
             }
         }
 
+        T::regs().smpr().write_value(smpr);
+        T::regs().smpr2().write_value(smpr2);
+        T::regs().sqr1().write_value(sqr1);
+        T::regs().sqr2().write_value(sqr2);
+        T::regs().sqr3().write_value(sqr3);
+        T::regs().sqr4().write_value(sqr4);
         #[cfg(stm32g4)]
-        {
-            T::regs().cr().modify(|w| w.set_aden(false));
-            T::regs().difsel().write_value(difsel);
-            T::enable();
-        }
+        T::regs().difsel().write_value(difsel);
     }
 }
 
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 13f8a1544..74648cc21 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -192,10 +192,16 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
         #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
         channel.setup();
 
-        #[cfg(not(adc_v4))]
+        #[cfg(any(adc_v2, adc_v3, adc_g0, adc_h7rs, adc_u0, adc_u5, adc_wba, adc_c0))]
         T::enable();
         T::configure_sequence([((channel.channel(), channel.is_differential()), sample_time)].into_iter());
 
+        // On chips with differential channels, enable after configure_sequence to allow setting differential channels
+        //
+        // TODO: If hardware allows, enable after configure_sequence on all chips
+        #[cfg(any(adc_g4, adc_h5))]
+        T::enable();
+
         T::convert()
     }
 
@@ -229,10 +235,10 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
     /// Note: This is not very efficient as the ADC needs to be reconfigured for each read. Use
     /// `into_ring_buffered`, `into_ring_buffered_and_injected`
     ///
-    /// In STM32C0, channels bigger than 14 cannot be read using sequencer, so you have to use
-    /// either blocking reads or use the mechanism to read in HW order (CHSELRMOD=0).
-    ///
-    /// In addtion, on STM320, this method will panic if the channels are not passed in order
+    /// Note: Depending on hardware limitations, this method may require channels to be passed
+    /// in order or require the sequence to have the same sample time for all channnels, depending
+    /// on the number and properties of the channels in the sequence. This method will panic if
+    /// the hardware cannot deliver the requested configuration.
     pub async fn read(
         &mut self,
         rx_dma: embassy_hal_internal::Peri<'_, impl RxDma<T>>,
@@ -249,14 +255,20 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
             "Asynchronous read sequence cannot be more than 16 in length"
         );
 
-        // Ensure no conversions are ongoing and ADC is enabled.
+        // Ensure no conversions are ongoing
         T::stop();
+        #[cfg(any(adc_g0, adc_v3, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
         T::enable();
 
         T::configure_sequence(
             sequence.map(|(channel, sample_time)| ((channel.channel, channel.is_differential), sample_time)),
         );
 
+        // On chips with differential channels, enable after configure_sequence to allow setting differential channels
+        //
+        // TODO: If hardware allows, enable after configure_sequence on all chips
+        #[cfg(any(adc_g4, adc_h5))]
+        T::enable();
         T::configure_dma(ConversionMode::Singular);
 
         let request = rx_dma.request();
@@ -294,6 +306,11 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
     ///
     /// # Returns
     /// A `RingBufferedAdc<'a, T>` instance configured for continuous DMA-based sampling.
+    ///
+    /// Note: Depending on hardware limitations, this method may require channels to be passed
+    /// in order or require the sequence to have the same sample time for all channnels, depending
+    /// on the number and properties of the channels in the sequence. This method will panic if
+    /// the hardware cannot deliver the requested configuration.
     pub fn into_ring_buffered<'a>(
         self,
         dma: embassy_hal_internal::Peri<'a, impl RxDma<T>>,
@@ -307,15 +324,20 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
             sequence.len() <= 16,
             "Asynchronous read sequence cannot be more than 16 in length"
         );
-        // reset conversions and enable the adc
+        // Ensure no conversions are ongoing
         T::stop();
+        #[cfg(any(adc_g0, adc_v3, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
         T::enable();
 
-        //adc side setup
         T::configure_sequence(
             sequence.map(|(channel, sample_time)| ((channel.channel, channel.is_differential), sample_time)),
         );
 
+        // On chips with differential channels, enable after configure_sequence to allow setting differential channels
+        //
+        // TODO: If hardware allows, enable after configure_sequence on all chips
+        #[cfg(any(adc_g4, adc_h5))]
+        T::enable();
         T::configure_dma(ConversionMode::Repeated(mode));
 
         core::mem::forget(self);
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 81eb1e3ee..b270588c4 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -260,6 +260,9 @@ impl<T: Instance> super::SealedAnyInstance for T {
     }
 
     fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+        #[cfg(adc_h5)]
+        T::regs().cr().modify(|w| w.set_aden(false));
+
         // Set sequence length
         #[cfg(not(any(adc_g0, adc_u0)))]
         T::regs().sqr1().modify(|w| {
@@ -294,8 +297,11 @@ impl<T: Instance> super::SealedAnyInstance for T {
             #[cfg(adc_u0)]
             let mut channel_mask = 0;
 
+            #[cfg(adc_h5)]
+            let mut difsel = 0u32;
+
             // Configure channels and ranks
-            for (_i, ((channel, _), sample_time)) in sequence.enumerate() {
+            for (_i, ((channel, _is_differential), sample_time)) in sequence.enumerate() {
                 // RM0492, RM0481, etc.
                 // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
                 #[cfg(any(adc_h5, adc_h7rs))]
@@ -357,12 +363,20 @@ impl<T: Instance> super::SealedAnyInstance for T {
                     _ => unreachable!(),
                 }
 
+                #[cfg(adc_h5)]
+                {
+                    difsel |= (_is_differential as u32) << channel;
+                }
+
                 #[cfg(adc_u0)]
                 {
                     channel_mask |= 1 << channel;
                 }
             }
 
+            #[cfg(adc_h5)]
+            T::regs().difsel().write(|w| w.set_difsel(difsel));
+
             // On G0 and U0 enabled channels are sampled from 0 to last channel.
             // It is possible to add up to 8 sequences if CHSELRMOD = 1.
             // However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
diff --git a/embassy-stm32/src/rtc/low_power.rs b/embassy-stm32/src/rtc/low_power.rs
index e5bf30927..f049d6b12 100644
--- a/embassy-stm32/src/rtc/low_power.rs
+++ b/embassy-stm32/src/rtc/low_power.rs
@@ -3,6 +3,7 @@ use embassy_time::{Duration, TICK_HZ};
 
 use super::{DateTimeError, Rtc, RtcError, bcd2_to_byte};
 use crate::interrupt::typelevel::Interrupt;
+use crate::pac::rtc::vals::Wucksel;
 use crate::peripherals::RTC;
 use crate::rtc::{RtcTimeProvider, SealedInstance};
 
@@ -58,60 +59,16 @@ impl core::ops::Sub for RtcInstant {
     }
 }
 
-#[repr(u8)]
-#[derive(Clone, Copy, Debug)]
-pub(crate) enum WakeupPrescaler {
-    Div2 = 2,
-    Div4 = 4,
-    Div8 = 8,
-    Div16 = 16,
-}
-
-#[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba, stm32wlex
-))]
-impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
-    fn from(val: WakeupPrescaler) -> Self {
-        use crate::pac::rtc::vals::Wucksel;
-
-        match val {
-            WakeupPrescaler::Div2 => Wucksel::DIV2,
-            WakeupPrescaler::Div4 => Wucksel::DIV4,
-            WakeupPrescaler::Div8 => Wucksel::DIV8,
-            WakeupPrescaler::Div16 => Wucksel::DIV16,
-        }
-    }
-}
-
-#[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba, stm32wlex
-))]
-impl From<crate::pac::rtc::vals::Wucksel> for WakeupPrescaler {
-    fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
-        use crate::pac::rtc::vals::Wucksel;
-
-        match val {
-            Wucksel::DIV2 => WakeupPrescaler::Div2,
-            Wucksel::DIV4 => WakeupPrescaler::Div4,
-            Wucksel::DIV8 => WakeupPrescaler::Div8,
-            Wucksel::DIV16 => WakeupPrescaler::Div16,
-            _ => unreachable!(),
-        }
-    }
-}
-
-impl WakeupPrescaler {
-    pub fn compute_min(val: u32) -> Self {
-        *[
-            WakeupPrescaler::Div2,
-            WakeupPrescaler::Div4,
-            WakeupPrescaler::Div8,
-            WakeupPrescaler::Div16,
-        ]
-        .iter()
-        .find(|psc| **psc as u32 > val)
-        .unwrap_or(&WakeupPrescaler::Div16)
-    }
+fn wucksel_compute_min(val: u32) -> (Wucksel, u32) {
+    *[
+        (Wucksel::DIV2, 2),
+        (Wucksel::DIV4, 4),
+        (Wucksel::DIV8, 8),
+        (Wucksel::DIV16, 16),
+    ]
+    .iter()
+    .find(|(_, psc)| *psc as u32 > val)
+    .unwrap_or(&(Wucksel::DIV16, 16))
 }
 
 impl Rtc {
@@ -138,7 +95,7 @@ impl Rtc {
         let requested_duration = requested_duration.as_ticks().clamp(0, u32::MAX as u64);
         let rtc_hz = Self::frequency().0 as u64;
         let rtc_ticks = requested_duration * rtc_hz / TICK_HZ;
-        let prescaler = WakeupPrescaler::compute_min((rtc_ticks / u16::MAX as u64) as u32);
+        let (wucksel, prescaler) = wucksel_compute_min((rtc_ticks / u16::MAX as u64) as u32);
 
         // adjust the rtc ticks to the prescaler and subtract one rtc tick
         let rtc_ticks = rtc_ticks / prescaler as u64;
@@ -159,7 +116,7 @@ impl Rtc {
                 while !regs.icsr().read().wutwf() {}
             }
 
-            regs.cr().modify(|w| w.set_wucksel(prescaler.into()));
+            regs.cr().modify(|w| w.set_wucksel(wucksel));
             regs.wutr().write(|w| w.set_wut(rtc_ticks));
             regs.cr().modify(|w| w.set_wute(true));
             regs.cr().modify(|w| w.set_wutie(true));
diff --git a/embassy-stm32/src/sai/mod.rs b/embassy-stm32/src/sai/mod.rs
index 726d1729a..ce4bc43c3 100644
--- a/embassy-stm32/src/sai/mod.rs
+++ b/embassy-stm32/src/sai/mod.rs
@@ -391,7 +391,7 @@ pub struct Config {
     pub frame_sync_polarity: FrameSyncPolarity,
     pub frame_sync_active_level_length: word::U7,
     pub frame_sync_definition: FrameSyncDefinition,
-    pub frame_length: u8,
+    pub frame_length: u16,
     pub clock_strobe: ClockStrobe,
     pub output_drive: OutputDrive,
     pub master_clock_divider: Option<MasterClockDivider>,
@@ -696,7 +696,7 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
             w.set_fspol(config.frame_sync_polarity.fspol());
             w.set_fsdef(config.frame_sync_definition.fsdef());
             w.set_fsall(config.frame_sync_active_level_length.0 as u8 - 1);
-            w.set_frl(config.frame_length - 1);
+            w.set_frl((config.frame_length - 1).try_into().unwrap());
         });
 
         ch.slotr().modify(|w| {
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index 7db51d72e..bc34892ee 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -196,6 +196,11 @@ fn calc_now(period: u32, counter: u16) -> u64 {
     ((period as u64) << 15) + ((counter as u32 ^ ((period & 1) << 15)) as u64)
 }
 
+#[cfg(feature = "low-power")]
+fn calc_period_counter(ticks: u64) -> (u32, u16) {
+    (2 * (ticks >> 16) as u32 + (ticks as u16 >= 0x8000) as u32, ticks as u16)
+}
+
 struct AlarmState {
     timestamp: Cell<u64>,
 }
@@ -358,34 +363,10 @@ impl RtcDriver {
     #[cfg(feature = "low-power")]
     /// Add the given offset to the current time
     fn add_time(&self, offset: embassy_time::Duration, cs: CriticalSection) {
-        let offset = offset.as_ticks();
-        let cnt = regs_gp16().cnt().read().cnt() as u32;
-        let period = self.period.load(Ordering::SeqCst);
-
-        // Correct the race, if it exists
-        let period = if period & 1 == 1 && cnt < u16::MAX as u32 / 2 {
-            period + 1
-        } else {
-            period
-        };
-
-        // Normalize to the full overflow
-        let period = (period / 2) * 2;
-
-        // Add the offset
-        let period = period + 2 * (offset / u16::MAX as u64) as u32;
-        let cnt = cnt + (offset % u16::MAX as u64) as u32;
-
-        let (cnt, period) = if cnt > u16::MAX as u32 {
-            (cnt - u16::MAX as u32, period + 2)
-        } else {
-            (cnt, period)
-        };
-
-        let period = if cnt > u16::MAX as u32 / 2 { period + 1 } else { period };
+        let (period, counter) = calc_period_counter(self.now() + offset.as_ticks());
 
         self.period.store(period, Ordering::SeqCst);
-        regs_gp16().cnt().write(|w| w.set_cnt(cnt as u16));
+        regs_gp16().cnt().write(|w| w.set_cnt(counter));
 
         // Now, recompute alarm
         let alarm = self.alarm.borrow(cs);
diff --git a/examples/stm32h723/src/bin/spdifrx.rs b/examples/stm32h723/src/bin/spdifrx.rs
index cdbd69b89..5c29602c6 100644
--- a/examples/stm32h723/src/bin/spdifrx.rs
+++ b/examples/stm32h723/src/bin/spdifrx.rs
@@ -167,7 +167,7 @@ fn new_sai_transmitter<'d>(
     sai_config.slot_count = hal::sai::word::U4(CHANNEL_COUNT as u8);
     sai_config.slot_enable = 0xFFFF; // All slots
     sai_config.data_size = sai::DataSize::Data32;
-    sai_config.frame_length = (CHANNEL_COUNT * 32) as u8;
+    sai_config.frame_length = (CHANNEL_COUNT * 32) as u16;
     sai_config.master_clock_divider = None;
 
     let (sub_block_tx, _) = hal::sai::split_subblocks(sai);