diff options
| author | Peter Krull <[email protected]> | 2024-09-19 20:07:08 +0200 |
|---|---|---|
| committer | Peter Krull <[email protected]> | 2024-09-19 20:07:08 +0200 |
| commit | 3aeeeb0d784d843b521b4b8b222114ef7ba71363 (patch) | |
| tree | f27cc7fd633e7fa4742870e99f623ac49734fcc1 | |
| parent | 4fcc8e39d6b3e486d2b94aa45d255d9c645d028a (diff) | |
stm32: Start DMA before clearing, avoid panic in updater ringbuffer impl
| -rw-r--r-- | embassy-stm32/src/usart/ringbuffered.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs index 2d9c63820..75834bf37 100644 --- a/embassy-stm32/src/usart/ringbuffered.rs +++ b/embassy-stm32/src/usart/ringbuffered.rs | |||
| @@ -81,9 +81,9 @@ impl<'d> RingBufferedUartRx<'d> { | |||
| 81 | /// Note: This is also done automatically by [`read()`] if required. | 81 | /// Note: This is also done automatically by [`read()`] if required. |
| 82 | pub fn start_uart(&mut self) { | 82 | pub fn start_uart(&mut self) { |
| 83 | // Clear the buffer so that it is ready to receive data | 83 | // Clear the buffer so that it is ready to receive data |
| 84 | self.ring_buf.clear(); | ||
| 85 | compiler_fence(Ordering::SeqCst); | 84 | compiler_fence(Ordering::SeqCst); |
| 86 | self.ring_buf.start(); | 85 | self.ring_buf.start(); |
| 86 | self.ring_buf.clear(); | ||
| 87 | 87 | ||
| 88 | let r = self.info.regs; | 88 | let r = self.info.regs; |
| 89 | // clear all interrupts and DMA Rx Request | 89 | // clear all interrupts and DMA Rx Request |
