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| author | Rogan Morrow <[email protected]> | 2025-02-28 12:28:57 +1100 |
|---|---|---|
| committer | Rogan Morrow <[email protected]> | 2025-02-28 12:28:57 +1100 |
| commit | 3b37c79331c191a5153bbe4ac7e464150c714f13 (patch) | |
| tree | 2fa88937df73d6a6227d13d462437da0a758ecee | |
| parent | 17301c00e986c5b8536435ea31ebf5aaf13aed17 (diff) | |
only clear idle flag
| -rw-r--r-- | embassy-stm32/src/usart/ringbuffered.rs | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs index 560ce4e8f..2a59cdcb4 100644 --- a/embassy-stm32/src/usart/ringbuffered.rs +++ b/embassy-stm32/src/usart/ringbuffered.rs | |||
| @@ -254,7 +254,9 @@ fn clear_idle_flag(r: Regs) -> Sr { | |||
| 254 | 254 | ||
| 255 | // This read also clears the error and idle interrupt flags on v1. | 255 | // This read also clears the error and idle interrupt flags on v1. |
| 256 | unsafe { rdr(r).read_volatile() }; | 256 | unsafe { rdr(r).read_volatile() }; |
| 257 | clear_interrupt_flags(r, sr); | 257 | let mut clear_idle = regs::Icr(0); |
| 258 | clear_idle.set_idle(true); | ||
| 259 | r.icr().write_value(clear_idle); | ||
| 258 | 260 | ||
| 259 | r.cr1().modify(|w| w.set_idleie(true)); | 261 | r.cr1().modify(|w| w.set_idleie(true)); |
| 260 | 262 | ||