WIP: add u5 adc4

5 files changed, 450 insertions, 17 deletions

diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 19cf193d9..e4cd001e6 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -1188,13 +1188,12 @@ fn main() {
     // ========
     // Generate dma_trait_impl!
 
-    let signals: HashMap<_, _> = [
+    let mut signals: HashMap<_, _> = [
         // (kind, signal) => trait
         (("adc", "ADC"), quote!(crate::adc::RxDma)),
         (("adc", "ADC1"), quote!(crate::adc::RxDma)),
         (("adc", "ADC2"), quote!(crate::adc::RxDma)),
         (("adc", "ADC3"), quote!(crate::adc::RxDma)),
-        (("adc", "ADC4"), quote!(crate::adc::RxDma)),
         (("ucpd", "RX"), quote!(crate::ucpd::RxDma)),
         (("ucpd", "TX"), quote!(crate::ucpd::TxDma)),
         (("usart", "RX"), quote!(crate::usart::RxDma)),
@@ -1228,6 +1227,12 @@ fn main() {
     ]
     .into();
 
+    if chip_name.starts_with("stm32u5") {
+        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma4));
+    } else {
+        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma));
+    }
+
     for p in METADATA.peripherals {
         if let Some(regs) = &p.registers {
             // FIXME: stm32u5a crash on Cordic driver
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 3bd7c793d..80c942816 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -25,6 +25,10 @@ pub use _version::*;
 #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
 use embassy_sync::waitqueue::AtomicWaker;
 
+#[cfg(adc_u5)]
+#[path = "u5_adc4.rs"]
+pub mod adc4;
+
 pub use crate::pac::adc::vals;
 #[cfg(not(any(adc_f1, adc_f3_v2)))]
 pub use crate::pac::adc::vals::Res as Resolution;
@@ -32,6 +36,8 @@ pub use crate::pac::adc::vals::SampleTime;
 use crate::peripherals;
 
 dma_trait!(RxDma, Instance);
+#[cfg(adc_u5)]
+dma_trait!(RxDma4, adc4::Instance);
 
 /// Analog to Digital driver.
 pub struct Adc<'d, T: Instance> {
@@ -159,6 +165,38 @@ impl<T: Instance> SealedAdcChannel<T> for AnyAdcChannel<T> {
     }
 }
 
+#[cfg(adc_u5)]
+foreach_adc!(
+    (ADC4, $common_inst:ident, $clock:ident) => {
+        impl crate::adc::adc4::SealedInstance for peripherals::ADC4 {
+            fn regs() -> crate::pac::adc::Adc4 {
+                crate::pac::ADC4
+            }
+        }
+
+        impl crate::adc::adc4::Instance for peripherals::ADC4 {
+            type Interrupt = crate::_generated::peripheral_interrupts::ADC4::GLOBAL;
+        }
+    };
+
+    ($inst:ident, $common_inst:ident, $clock:ident) => {
+        impl crate::adc::SealedInstance for peripherals::$inst {
+            fn regs() -> crate::pac::adc::Adc {
+                crate::pac::$inst
+            }
+
+            fn common_regs() -> crate::pac::adccommon::AdcCommon {
+                return crate::pac::$common_inst
+            }
+        }
+
+        impl crate::adc::Instance for peripherals::$inst {
+            type Interrupt = crate::_generated::peripheral_interrupts::$inst::GLOBAL;
+        }
+    };
+);
+
+#[cfg(not(adc_u5))]
 foreach_adc!(
     ($inst:ident, $common_inst:ident, $clock:ident) => {
         impl crate::adc::SealedInstance for peripherals::$inst {
diff --git a/embassy-stm32/src/adc/u5.rs b/embassy-stm32/src/adc/u5.rs
index a86638a60..314cb02e2 100644
--- a/embassy-stm32/src/adc/u5.rs
+++ b/embassy-stm32/src/adc/u5.rs
@@ -11,7 +11,7 @@ use crate::{pac, rcc, Peripheral};
 
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
 
-const VREF_CHANNEL: u8 = 1;
+const VREF_CHANNEL: u8 = 0;
 const VBAT_CHANNEL: u8 = 18;
 const TEMP_CHANNEL: u8 = 19;
 
@@ -132,23 +132,9 @@ pub enum Averaging {
     Samples1024,
 }
 
-// TODO
-// impl Instance for ADC4 {
-
-// }
-
 impl<'d, T: Instance> Adc<'d, T> {
     /// Create a new ADC driver.
     pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
-        // move to u5 init (RCC)?
-        PWR.svmcr().modify(|w| {
-            w.set_avm1en(true);
-        });
-        while !PWR.svmsr().read().vdda1rdy() {}
-        PWR.svmcr().modify(|w| {
-            w.set_asv(true);
-        });
-
         embassy_hal_internal::into_ref!(adc);
         rcc::enable_and_reset::<T>();
         let prescaler = Prescaler::from_ker_ck(T::frequency());
diff --git a/embassy-stm32/src/adc/u5_adc4.rs b/embassy-stm32/src/adc/u5_adc4.rs
new file mode 100644
index 000000000..5dec0caa9
--- /dev/null
+++ b/embassy-stm32/src/adc/u5_adc4.rs
@@ -0,0 +1,384 @@
+pub use crate::pac::adc::vals::Adc4Res as Resolution;
+pub use crate::pac::adc::vals::Adc4SampleTime as SampleTime;
+pub use crate::pac::adc::vals::Adc4Presc as Presc;
+pub use crate::pac::adc::regs::Adc4Chselrmod0;
+
+#[allow(unused)]
+use pac::adc::vals::{Adc4Exten, Adc4OversamplingRatio};
+
+use super::{
+    blocking_delay_us, AdcChannel, SealedAdcChannel
+};
+use crate::time::Hertz;
+use crate::{pac, rcc, Peripheral};
+
+const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
+
+/// Default VREF voltage used for sample conversion to millivolts.
+pub const VREF_DEFAULT_MV: u32 = 3300;
+/// VREF voltage used for factory calibration of VREFINTCAL register.
+pub const VREF_CALIB_MV: u32 = 3300;
+
+const VREF_CHANNEL: u8 = 0;
+const VCORE_CHANNEL: u8 = 12;
+const TEMP_CHANNEL: u8 = 13;
+const VBAT_CHANNEL: u8 = 14;
+const DAC_CHANNEL: u8 = 21;
+
+// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
+/// Internal voltage reference channel.
+pub struct VrefInt;
+impl<T: Instance> AdcChannel<T> for VrefInt {}
+impl<T: Instance> SealedAdcChannel<T> for VrefInt {
+    fn channel(&self) -> u8 {
+        VREF_CHANNEL
+    }
+}
+
+/// Internal temperature channel.
+pub struct Temperature;
+impl<T: Instance> AdcChannel<T> for Temperature {}
+impl<T: Instance> SealedAdcChannel<T> for Temperature {
+    fn channel(&self) -> u8 {
+        TEMP_CHANNEL
+    }
+}
+
+/// Internal battery voltage channel.
+pub struct Vbat;
+impl<T: Instance> AdcChannel<T> for Vbat {}
+impl<T: Instance> SealedAdcChannel<T> for Vbat {
+    fn channel(&self) -> u8 {
+        VBAT_CHANNEL
+    }
+}
+
+/// Internal DAC channel.
+pub struct Dac;
+impl<T: Instance> AdcChannel<T> for Dac {}
+impl<T: Instance> SealedAdcChannel<T> for Dac {
+    fn channel(&self) -> u8 {
+        DAC_CHANNEL
+    }
+}
+
+/// Internal Vcore channel.
+pub struct Vcore;
+impl<T: Instance> AdcChannel<T> for Vcore {}
+impl<T: Instance> SealedAdcChannel<T> for Vcore {
+    fn channel(&self) -> u8 {
+        VCORE_CHANNEL
+    }
+}
+
+pub enum DacChannel {
+    OUT1,
+    OUT2
+}
+
+/// Number of samples used for averaging.
+pub enum Averaging {
+    Disabled,
+    Samples2,
+    Samples4,
+    Samples8,
+    Samples16,
+    Samples32,
+    Samples64,
+    Samples128,
+    Samples256,
+}
+
+pub const fn resolution_to_max_count(res: Resolution) -> u32 {
+    match res {
+        Resolution::BITS12 => (1 << 12) - 1,
+        Resolution::BITS10 => (1 << 10) - 1,
+        Resolution::BITS8 => (1 << 8) - 1,
+        Resolution::BITS6 => (1 << 6) - 1,
+        #[allow(unreachable_patterns)]
+        _ => core::unreachable!(),
+    }
+}
+
+// NOTE (unused): The prescaler enum closely copies the hardware capabilities,
+// but high prescaling doesn't make a lot of sense in the current implementation and is ommited.
+#[allow(unused)]
+enum Prescaler {
+    NotDivided,
+    DividedBy2,
+    DividedBy4,
+    DividedBy6,
+    DividedBy8,
+    DividedBy10,
+    DividedBy12,
+    DividedBy16,
+    DividedBy32,
+    DividedBy64,
+    DividedBy128,
+    DividedBy256,
+}
+
+impl Prescaler {
+    fn from_ker_ck(frequency: Hertz) -> Self {
+        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
+        match raw_prescaler {
+            0 => Self::NotDivided,
+            1 => Self::DividedBy2,
+            2..=3 => Self::DividedBy4,
+            4..=5 => Self::DividedBy6,
+            6..=7 => Self::DividedBy8,
+            8..=9 => Self::DividedBy10,
+            10..=11 => Self::DividedBy12,
+            _ => unimplemented!(),
+        }
+    }
+
+    fn divisor(&self) -> u32 {
+        match self {
+            Prescaler::NotDivided => 1,
+            Prescaler::DividedBy2 => 2,
+            Prescaler::DividedBy4 => 4,
+            Prescaler::DividedBy6 => 6,
+            Prescaler::DividedBy8 => 8,
+            Prescaler::DividedBy10 => 10,
+            Prescaler::DividedBy12 => 12,
+            Prescaler::DividedBy16 => 16,
+            Prescaler::DividedBy32 => 32,
+            Prescaler::DividedBy64 => 64,
+            Prescaler::DividedBy128 => 128,
+            Prescaler::DividedBy256 => 256,
+        }
+    }
+
+    fn presc(&self) -> Presc {
+        match self {
+            Prescaler::NotDivided => Presc::DIV1,
+            Prescaler::DividedBy2 => Presc::DIV2,
+            Prescaler::DividedBy4 => Presc::DIV4,
+            Prescaler::DividedBy6 => Presc::DIV6,
+            Prescaler::DividedBy8 => Presc::DIV8,
+            Prescaler::DividedBy10 => Presc::DIV10,
+            Prescaler::DividedBy12 => Presc::DIV12,
+            Prescaler::DividedBy16 => Presc::DIV16,
+            Prescaler::DividedBy32 => Presc::DIV32,
+            Prescaler::DividedBy64 => Presc::DIV64,
+            Prescaler::DividedBy128 => Presc::DIV128,
+            Prescaler::DividedBy256 => Presc::DIV256,
+        }
+    }
+}
+
+pub trait SealedInstance {
+    #[allow(unused)]
+    fn regs() -> crate::pac::adc::Adc4;
+}
+
+pub trait Instance: SealedInstance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {
+    type Interrupt: crate::interrupt::typelevel::Interrupt;
+}
+
+pub struct Adc4<'d, T: Instance> {
+    adc: crate::PeripheralRef<'d, T>,
+}
+
+impl<'d, T: Instance> Adc4<'d, T> {
+    /// Create a new ADC driver.
+    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
+        embassy_hal_internal::into_ref!(adc);
+        rcc::enable_and_reset::<T>();
+        let prescaler = Prescaler::from_ker_ck(T::frequency());
+
+        T::regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+
+        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
+        info!("ADC4 frequency set to {} Hz", frequency.0);
+
+        if frequency > MAX_ADC_CLK_FREQ {
+            panic!("Maximal allowed frequency for ADC4 is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
+        }
+
+        let mut s = Self {
+            adc,
+        };
+
+        s.power_up();
+
+        s.calibrate();
+        blocking_delay_us(1);
+
+        s.enable();
+        s.configure();
+
+        s
+    }
+
+    fn power_up(&mut self) {
+        T::regs().isr().modify(|reg| {
+            reg.set_ldordy(true);
+        });
+        T::regs().cr().modify(|reg| {
+            reg.set_advregen(true);
+        });
+        while !T::regs().isr().read().ldordy() { };
+
+        T::regs().isr().modify(|reg| {
+            reg.set_ldordy(true);
+        });
+    }
+
+    fn calibrate(&mut self) {
+        T::regs().cr().modify(|w| w.set_adcal(true));
+        while T::regs().cr().read().adcal() {}
+        T::regs().isr().modify(|w| w.set_eocal(true));
+    }
+
+    fn enable(&mut self) {
+        T::regs().isr().write(|w| w.set_adrdy(true));
+        T::regs().cr().modify(|w| w.set_aden(true));
+        while !T::regs().isr().read().adrdy() {}
+        T::regs().isr().write(|w| w.set_adrdy(true));
+    }
+
+    fn configure(&mut self) {
+        // single conversion mode, software trigger
+        T::regs().cfgr1().modify(|w| {
+            w.set_cont(false);
+            w.set_exten(Adc4Exten::DISABLED);
+        });
+
+        // only use one channel at the moment
+        T::regs().smpr().modify(|w| {
+            for i in 0..24 {
+                w.set_smpsel(i, false);
+            }
+        });
+    }
+
+    /// Enable reading the voltage reference internal channel.
+    pub fn enable_vrefint(&self) -> VrefInt {
+        T::regs().ccr().modify(|reg| {
+            reg.set_vrefen(true);
+        });
+
+        VrefInt {}
+    }
+
+    /// Enable reading the temperature internal channel.
+    pub fn enable_temperature(&self) -> Temperature {
+        T::regs().ccr().modify(|reg| {
+            reg.set_vsensesel(true);
+        });
+
+        Temperature {}
+    }
+
+    /// Enable reading the vbat internal channel.
+    pub fn enable_vbat(&self) -> Vbat {
+        T::regs().ccr().modify(|reg| {
+            reg.set_vbaten(true);
+        });
+
+        Vbat {}
+    }
+
+    /// Enable reading the vbat internal channel.
+    pub fn enable_vcore(&self) -> Vcore {
+        Vcore {}
+    }
+
+    /// Enable reading the vbat internal channel.
+    pub fn enable_dac_channel(&self, dac: DacChannel) -> Dac {
+        let mux;
+        match dac {
+            DacChannel::OUT1 => {mux = false},
+            DacChannel::OUT2 => {mux = true}
+        }
+        T::regs().or().modify(|w| w.set_chn21sel(mux));
+        Dac {}
+    }
+
+    /// Set the ADC sample time.
+    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
+        T::regs().smpr().modify(|w| {
+            w.set_smp(0, sample_time);
+        });
+    }
+
+    /// Get the ADC sample time.
+    pub fn sample_time(&self) -> SampleTime {
+        T::regs().smpr().read().smp(0)
+    }
+
+    /// Set the ADC resolution.
+    pub fn set_resolution(&mut self, resolution: Resolution) {
+        T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
+    }
+
+    /// Set hardware averaging.
+    pub fn set_averaging(&mut self, averaging: Averaging) {
+        let (enable, samples, right_shift) = match averaging {
+            Averaging::Disabled => (false, Adc4OversamplingRatio::OVERSAMPLE2X, 0),
+            Averaging::Samples2 => (true, Adc4OversamplingRatio::OVERSAMPLE2X, 1),
+            Averaging::Samples4 => (true, Adc4OversamplingRatio::OVERSAMPLE4X, 2),
+            Averaging::Samples8 => (true, Adc4OversamplingRatio::OVERSAMPLE8X, 3),
+            Averaging::Samples16 => (true, Adc4OversamplingRatio::OVERSAMPLE16X, 4),
+            Averaging::Samples32 => (true, Adc4OversamplingRatio::OVERSAMPLE32X, 5),
+            Averaging::Samples64 => (true, Adc4OversamplingRatio::OVERSAMPLE64X, 6),
+            Averaging::Samples128 => (true, Adc4OversamplingRatio::OVERSAMPLE128X, 7),
+            Averaging::Samples256 => (true, Adc4OversamplingRatio::OVERSAMPLE256X, 8),
+        };
+
+        T::regs().cfgr2().modify(|reg| {
+            reg.set_ovsr(samples);
+            reg.set_ovss(right_shift);
+            reg.set_ovse(enable)
+        })
+    }
+
+    /// Perform a single conversion.
+    fn convert(&mut self) -> u16 {
+        T::regs().isr().modify(|reg| {
+            reg.set_eos(true);
+            reg.set_eoc(true);
+        });
+
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+
+        while !T::regs().isr().read().eos() {
+            // spin
+        }
+
+        T::regs().dr().read().0 as u16
+    }
+
+    /// Read an ADC channel.
+    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+        self.read_channel(channel)
+    }
+
+    fn configure_channel(channel: &mut impl AdcChannel<T>) {
+        channel.setup();
+        T::regs().chselrmod0().write_value(Adc4Chselrmod0(0_u32));
+        T::regs().chselrmod0().modify(|w| {
+            w.set_chsel(channel.channel() as usize, true);
+        });
+    }
+
+    fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+        Self::configure_channel(channel);
+        let ret = self.convert();
+        ret
+    }
+
+    fn cancel_conversions() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(true);
+            });
+            while T::regs().cr().read().adstart() {}
+        }
+    }
+}
\ No newline at end of file
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 451f595e0..232373087 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -218,6 +218,10 @@ pub struct Config {
     #[cfg(any(stm32l4, stm32l5, stm32u5))]
     pub enable_independent_io_supply: bool,
 
+    /// On the U5 series all analog peripherals are powere by a separate supply.
+    #[cfg(stm32u5)]
+    pub enable_independent_analog_supply: bool,
+
     /// BDMA interrupt priority.
     ///
     /// Defaults to P0 (highest).
@@ -257,6 +261,8 @@ impl Default for Config {
             enable_debug_during_sleep: true,
             #[cfg(any(stm32l4, stm32l5, stm32u5))]
             enable_independent_io_supply: true,
+            #[cfg(stm32u5)]
+            enable_independent_analog_supply: true,
             #[cfg(bdma)]
             bdma_interrupt_priority: Priority::P0,
             #[cfg(dma)]
@@ -464,6 +470,20 @@ fn init_hw(config: Config) -> Peripherals {
             crate::pac::PWR.svmcr().modify(|w| {
                 w.set_io2sv(config.enable_independent_io_supply);
             });
+            if config.enable_independent_analog_supply {
+                crate::pac::PWR.svmcr().modify(|w| {
+                    w.set_avm1en(true);
+                });
+                while !crate::pac::PWR.svmsr().read().vdda1rdy() {}
+                crate::pac::PWR.svmcr().modify(|w| {
+                    w.set_asv(true);
+                });
+            } else {
+                crate::pac::PWR.svmcr().modify(|w| {
+                    w.set_avm1en(false);
+                    w.set_avm2en(false);
+                });
+            }
         }
 
         // dead battery functionality is still present on these