diff options
| author | Eric Yanush <[email protected]> | 2024-04-22 14:01:48 -0600 |
|---|---|---|
| committer | Eric Yanush <[email protected]> | 2024-04-22 14:01:48 -0600 |
| commit | 3e00c1ac52ac847db44f83b6d94d493356a990ff (patch) | |
| tree | 107bba22108d2de9afeac41faada581bed568a8d | |
| parent | 68a4fd8f4a18a33a9045d7128a39d8dff5652491 (diff) | |
rustfmt whitespace fixes
| -rw-r--r-- | embassy-stm32/src/can/bxcan/mod.rs | 2 | ||||
| -rw-r--r-- | embassy-stm32/src/can/bxcan/registers.rs | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/embassy-stm32/src/can/bxcan/mod.rs b/embassy-stm32/src/can/bxcan/mod.rs index c524c68a9..fa408c260 100644 --- a/embassy-stm32/src/can/bxcan/mod.rs +++ b/embassy-stm32/src/can/bxcan/mod.rs | |||
| @@ -76,7 +76,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::SCEInterrupt> for SceInterrup | |||
| 76 | // Disable the interrupt, but don't acknowledge the error, so that it can be | 76 | // Disable the interrupt, but don't acknowledge the error, so that it can be |
| 77 | // forwarded off the the bus message consumer. If we don't provide some way for | 77 | // forwarded off the the bus message consumer. If we don't provide some way for |
| 78 | // downstream code to determine that it has already provided this bus error instance | 78 | // downstream code to determine that it has already provided this bus error instance |
| 79 | // to the bus message consumer, we are doomed to re-provide a single error instance for | 79 | // to the bus message consumer, we are doomed to re-provide a single error instance for |
| 80 | // an indefinite amount of time. | 80 | // an indefinite amount of time. |
| 81 | let ier = T::regs().ier(); | 81 | let ier = T::regs().ier(); |
| 82 | ier.modify(|i| i.set_errie(false)); | 82 | ier.modify(|i| i.set_errie(false)); |
diff --git a/embassy-stm32/src/can/bxcan/registers.rs b/embassy-stm32/src/can/bxcan/registers.rs index 225b25d8a..446f3ad6f 100644 --- a/embassy-stm32/src/can/bxcan/registers.rs +++ b/embassy-stm32/src/can/bxcan/registers.rs | |||
| @@ -148,10 +148,10 @@ impl Registers { | |||
| 148 | if !self.0.msr().read().erri() { | 148 | if !self.0.msr().read().erri() { |
| 149 | // This ensures that once a single error instance has | 149 | // This ensures that once a single error instance has |
| 150 | // been acknowledged and forwared to the bus message consumer | 150 | // been acknowledged and forwared to the bus message consumer |
| 151 | // we don't continue to re-forward the same error occurrance for an | 151 | // we don't continue to re-forward the same error occurrance for an |
| 152 | // in-definite amount of time. | 152 | // in-definite amount of time. |
| 153 | return None; | 153 | return None; |
| 154 | } | 154 | } |
| 155 | 155 | ||
| 156 | // Since we have not already acknowledge the error, and the interrupt was | 156 | // Since we have not already acknowledge the error, and the interrupt was |
| 157 | // disabled in the ISR, we will acknowledge the current error and re-enable the interrupt | 157 | // disabled in the ISR, we will acknowledge the current error and re-enable the interrupt |
