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authorxoviat <[email protected]>2021-03-20 23:51:36 -0500
committerGitHub <[email protected]>2021-03-20 23:51:36 -0500
commit3e4e292cb70394a05b007e98e6fc9b513f63b7b2 (patch)
treeb4712270aeb26aea8fea1f6fe0ed3d0decf732c8
parenta66ee4a8242647ee1c9f1e80789a2eaeab128aaf (diff)
parent556942a6bf0933921f33bfcb0155fbabf33b59c6 (diff)
Merge pull request #100 from xoviat/serial-idle
implement idle on read
-rw-r--r--.vscode/settings.json1
-rw-r--r--embassy-stm32f4/Cargo.toml1
-rw-r--r--embassy-stm32f4/src/serial.rs42
3 files changed, 32 insertions, 12 deletions
diff --git a/.vscode/settings.json b/.vscode/settings.json
index 8a292c0be..58ef9d8af 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -1,6 +1,7 @@
1{ 1{
2 "rust-analyzer.assist.importMergeBehavior": "last", 2 "rust-analyzer.assist.importMergeBehavior": "last",
3 "editor.formatOnSave": true, 3 "editor.formatOnSave": true,
4 "rust.target": "thumbv7em-none-eabihf",
4 "rust-analyzer.cargo.allFeatures": false, 5 "rust-analyzer.cargo.allFeatures": false,
5 "rust-analyzer.checkOnSave.allFeatures": false, 6 "rust-analyzer.checkOnSave.allFeatures": false,
6 "rust-analyzer.checkOnSave.allTargets": false, 7 "rust-analyzer.checkOnSave.allTargets": false,
diff --git a/embassy-stm32f4/Cargo.toml b/embassy-stm32f4/Cargo.toml
index ae3273d67..c132d7c99 100644
--- a/embassy-stm32f4/Cargo.toml
+++ b/embassy-stm32f4/Cargo.toml
@@ -36,6 +36,7 @@ defmt = { version = "0.2.0", optional = true }
36log = { version = "0.4.11", optional = true } 36log = { version = "0.4.11", optional = true }
37cortex-m-rt = "0.6.13" 37cortex-m-rt = "0.6.13"
38cortex-m = "0.7.1" 38cortex-m = "0.7.1"
39futures = { version = "0.3.5", default-features = false, features = ["async-await"] }
39embedded-hal = { version = "0.2.4" } 40embedded-hal = { version = "0.2.4" }
40embedded-dma = { version = "0.1.2" } 41embedded-dma = { version = "0.1.2" }
41stm32f4xx-hal = { version = "0.8.3", features = ["rt", "can"], git = "https://github.com/stm32-rs/stm32f4xx-hal.git"} 42stm32f4xx-hal = { version = "0.8.3", features = ["rt", "can"], git = "https://github.com/stm32-rs/stm32f4xx-hal.git"}
diff --git a/embassy-stm32f4/src/serial.rs b/embassy-stm32f4/src/serial.rs
index 381e0f5e4..bed89288e 100644
--- a/embassy-stm32f4/src/serial.rs
+++ b/embassy-stm32f4/src/serial.rs
@@ -7,6 +7,8 @@
7use core::future::Future; 7use core::future::Future;
8use core::marker::PhantomData; 8use core::marker::PhantomData;
9 9
10use futures::{select_biased, FutureExt};
11
10use embassy::interrupt::Interrupt; 12use embassy::interrupt::Interrupt;
11use embassy::traits::uart::{Error, Uart}; 13use embassy::traits::uart::{Error, Uart};
12use embassy::util::InterruptFuture; 14use embassy::util::InterruptFuture;
@@ -19,7 +21,7 @@ use crate::hal::{
19 rcc::Clocks, 21 rcc::Clocks,
20 serial, 22 serial,
21 serial::config::{Config as SerialConfig, DmaConfig as SerialDmaConfig}, 23 serial::config::{Config as SerialConfig, DmaConfig as SerialDmaConfig},
22 serial::{Event as SerialEvent, Pins, Serial as HalSerial}, 24 serial::{Event as SerialEvent, Pins},
23}; 25};
24use crate::interrupt; 26use crate::interrupt;
25use crate::pac; 27use crate::pac;
@@ -29,14 +31,14 @@ pub struct Serial<
29 USART: PeriAddress<MemSize = u8> + WithInterrupt, 31 USART: PeriAddress<MemSize = u8> + WithInterrupt,
30 TSTREAM: Stream + WithInterrupt, 32 TSTREAM: Stream + WithInterrupt,
31 RSTREAM: Stream + WithInterrupt, 33 RSTREAM: Stream + WithInterrupt,
32 CHANNEL: dma::traits::Channel, 34 CHANNEL: Channel,
33> { 35> {
34 tx_stream: Option<TSTREAM>, 36 tx_stream: Option<TSTREAM>,
35 rx_stream: Option<RSTREAM>, 37 rx_stream: Option<RSTREAM>,
36 usart: Option<USART>, 38 usart: Option<USART>,
37 tx_int: TSTREAM::Interrupt, 39 tx_int: TSTREAM::Interrupt,
38 rx_int: RSTREAM::Interrupt, 40 rx_int: RSTREAM::Interrupt,
39 _usart_int: USART::Interrupt, 41 usart_int: USART::Interrupt,
40 channel: PhantomData<CHANNEL>, 42 channel: PhantomData<CHANNEL>,
41} 43}
42 44
@@ -68,12 +70,10 @@ where
68 PINS: Pins<USART>, 70 PINS: Pins<USART>,
69 { 71 {
70 config.dma = SerialDmaConfig::TxRx; 72 config.dma = SerialDmaConfig::TxRx;
71 let mut serial = HalSerial::new(usart, pins, config, clocks).unwrap();
72
73 serial.listen(SerialEvent::Idle);
74 // serial.listen(SerialEvent::Txe);
75 73
76 let (usart, _) = serial.release(); 74 let (usart, _) = serial::Serial::new(usart, pins, config, clocks)
75 .unwrap()
76 .release();
77 77
78 let (tx_stream, rx_stream) = streams; 78 let (tx_stream, rx_stream) = streams;
79 79
@@ -83,8 +83,8 @@ where
83 usart: Some(usart), 83 usart: Some(usart),
84 tx_int: tx_int, 84 tx_int: tx_int,
85 rx_int: rx_int, 85 rx_int: rx_int,
86 _usart_int: usart_int, 86 usart_int: usart_int,
87 channel: core::marker::PhantomData, 87 channel: PhantomData,
88 } 88 }
89 } 89 }
90} 90}
@@ -127,10 +127,10 @@ where
127 let fut = InterruptFuture::new(&mut self.tx_int); 127 let fut = InterruptFuture::new(&mut self.tx_int);
128 128
129 tx_transfer.start(|_usart| {}); 129 tx_transfer.start(|_usart| {});
130
131 fut.await; 130 fut.await;
132 131
133 let (tx_stream, usart, _buf, _) = tx_transfer.free(); 132 let (tx_stream, usart, _buf, _) = tx_transfer.free();
133
134 self.tx_stream.replace(tx_stream); 134 self.tx_stream.replace(tx_stream);
135 self.usart.replace(usart); 135 self.usart.replace(usart);
136 136
@@ -151,6 +151,15 @@ where
151 let usart = self.usart.take().unwrap(); 151 let usart = self.usart.take().unwrap();
152 152
153 async move { 153 async move {
154 unsafe {
155 /* __HAL_UART_ENABLE_IT(&uart->UartHandle, UART_IT_IDLE); */
156 (*USART::ptr()).cr1.modify(|_, w| w.idleie().set_bit());
157
158 /* __HAL_UART_CLEAR_IDLEFLAG(&uart->UartHandle); */
159 (*USART::ptr()).sr.read();
160 (*USART::ptr()).dr.read();
161 };
162
154 let mut rx_transfer = Transfer::init( 163 let mut rx_transfer = Transfer::init(
155 rx_stream, 164 rx_stream,
156 usart, 165 usart,
@@ -163,11 +172,20 @@ where
163 ); 172 );
164 173
165 let fut = InterruptFuture::new(&mut self.rx_int); 174 let fut = InterruptFuture::new(&mut self.rx_int);
175 let fut_idle = InterruptFuture::new(&mut self.usart_int);
166 176
167 rx_transfer.start(|_usart| {}); 177 rx_transfer.start(|_usart| {});
168 fut.await; 178
179 select_biased! {
180 () = fut.fuse() => {},
181 () = fut_idle.fuse() => {},
182 }
169 183
170 let (rx_stream, usart, _, _) = rx_transfer.free(); 184 let (rx_stream, usart, _, _) = rx_transfer.free();
185
186 unsafe {
187 (*USART::ptr()).cr1.modify(|_, w| w.idleie().clear_bit());
188 }
171 self.rx_stream.replace(rx_stream); 189 self.rx_stream.replace(rx_stream);
172 self.usart.replace(usart); 190 self.usart.replace(usart);
173 191