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authorEmilie Burgun <[email protected]>2024-03-26 17:27:02 +0100
committerEmilie Burgun <[email protected]>2024-03-26 17:27:02 +0100
commit402def86ee6a1d8695fc0a4cf157d1ffca7550d9 (patch)
tree116aa9a8b9c756dc3dcf634ab3c1d86354436c4e
parentca998c170f18c252e0d4c5a6aed1085113c27dd0 (diff)
Remove ad-hoc fixes for setting the IOSV bit to true
-rw-r--r--embassy-stm32/src/gpio.rs7
-rw-r--r--examples/stm32l4/src/bin/spe_adin1110_http_server.rs6
-rw-r--r--tests/stm32/src/common.rs7
3 files changed, 0 insertions, 20 deletions
diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index 33f22f676..214813a42 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -779,13 +779,6 @@ pub(crate) unsafe fn init(_cs: CriticalSection) {
779 <crate::peripherals::AFIO as crate::rcc::SealedRccPeripheral>::enable_and_reset_with_cs(_cs); 779 <crate::peripherals::AFIO as crate::rcc::SealedRccPeripheral>::enable_and_reset_with_cs(_cs);
780 780
781 crate::_generated::init_gpio(); 781 crate::_generated::init_gpio();
782
783 // Setting this bit is mandatory to use PG[15:2].
784 #[cfg(stm32u5)]
785 crate::pac::PWR.svmcr().modify(|w| {
786 w.set_io2sv(true);
787 w.set_io2vmen(true);
788 });
789} 782}
790 783
791impl<'d> embedded_hal_02::digital::v2::InputPin for Input<'d> { 784impl<'d> embedded_hal_02::digital::v2::InputPin for Input<'d> {
diff --git a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
index 343e09e68..77aa929ab 100644
--- a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
+++ b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
@@ -93,12 +93,6 @@ async fn main(spawner: Spawner) {
93 93
94 let dp = embassy_stm32::init(config); 94 let dp = embassy_stm32::init(config);
95 95
96 // RM0432rev9, 5.1.2: Independent I/O supply rail
97 // After reset, the I/Os supplied by VDDIO2 are logically and electrically isolated and
98 // therefore are not available. The isolation must be removed before using any I/O from
99 // PG[15:2], by setting the IOSV bit in the PWR_CR2 register, once the VDDIO2 supply is present
100 pac::PWR.cr2().modify(|w| w.set_iosv(true));
101
102 let reset_status = pac::RCC.bdcr().read().0; 96 let reset_status = pac::RCC.bdcr().read().0;
103 defmt::println!("bdcr before: 0x{:X}", reset_status); 97 defmt::println!("bdcr before: 0x{:X}", reset_status);
104 98
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index c379863a8..0e555efc8 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -251,13 +251,6 @@ define_peris!(
251); 251);
252 252
253pub fn config() -> Config { 253pub fn config() -> Config {
254 // Setting this bit is mandatory to use PG[15:2].
255 #[cfg(feature = "stm32u5a5zj")]
256 embassy_stm32::pac::PWR.svmcr().modify(|w| {
257 w.set_io2sv(true);
258 w.set_io2vmen(true);
259 });
260
261 #[allow(unused_mut)] 254 #[allow(unused_mut)]
262 let mut config = Config::default(); 255 let mut config = Config::default();
263 256