stm32/hash: Clear HMAC mode bit when hashing

Running a hash after a hmac would hang, the CR.MODE bit isn't cleared by
INIT.

Test it by running the test twice.

3 files changed, 15 insertions, 5 deletions

diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index 0c2d23246..9ad117312 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## Unreleased - ReleaseDate
 
 - fix: Fix vrefbuf building with log feature
+- fix: Fix performing a hash after performing a hmac
 
 ## 0.3.0 - 2025-08-12
 
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
index e62151bb5..a4c275242 100644
--- a/embassy-stm32/src/hash/mod.rs
+++ b/embassy-stm32/src/hash/mod.rs
@@ -198,6 +198,8 @@ impl<'d, T: Instance, M: Mode> Hash<'d, T, M> {
             if key.len() > 64 {
                 T::regs().cr().modify(|w| w.set_lkey(true));
             }
+        } else {
+            T::regs().cr().modify(|w| w.set_mode(false));
         }
 
         T::regs().cr().modify(|w| w.set_init(true));
diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs
index 52b84a499..2499f42ed 100644
--- a/tests/stm32/src/bin/hash.rs
+++ b/tests/stm32/src/bin/hash.rs
@@ -7,6 +7,7 @@ mod common;
 use common::*;
 use embassy_executor::Spawner;
 use embassy_stm32::hash::*;
+use embassy_stm32::mode::Blocking;
 use embassy_stm32::{bind_interrupts, hash, peripherals};
 use hmac::{Hmac, Mac};
 use sha2::{Digest, Sha224, Sha256};
@@ -32,11 +33,7 @@ bind_interrupts!(struct Irqs {
     HASH => hash::InterruptHandler<peripherals::HASH>;
 });
 
-#[embassy_executor::main]
-async fn main(_spawner: Spawner) {
-    let p: embassy_stm32::Peripherals = init();
-    let mut hw_hasher = Hash::new_blocking(p.HASH, Irqs);
-
+fn test_interrupt(hw_hasher: &mut Hash<'_, peripherals::HASH, Blocking>) {
     let test_1: &[u8] = b"as;dfhaslfhas;oifvnasd;nifvnhasd;nifvhndlkfghsd;nvfnahssdfgsdafgsasdfasdfasdfasdfasdfghjklmnbvcalskdjghalskdjgfbaslkdjfgbalskdjgbalskdjbdfhsdfhsfghsfghfgh";
     let test_2: &[u8] = b"fdhalksdjfhlasdjkfhalskdjfhgal;skdjfgalskdhfjgalskdjfglafgadfgdfgdafgaadsfgfgdfgadrgsyfthxfgjfhklhjkfgukhulkvhlvhukgfhfsrghzdhxyfufynufyuszeradrtydyytserr";
     let test_3: &[u8] = b"a.ewtkluGWEBR.KAJRBTA,RMNRBG,FDMGB.kger.tkasjrbt.akrjtba.krjtba.ktmyna,nmbvtyliasd;gdrtba,sfvs.kgjzshd.gkbsr.tksejb.SDkfBSE.gkfgb>ESkfbSE>gkJSBESE>kbSE>fk";
@@ -95,6 +92,16 @@ async fn main(_spawner: Spawner) {
     info!("Hardware HMAC: {:?}", hw_hmac);
     info!("Software HMAC: {:?}", sw_hmac[..]);
     defmt::assert!(hw_hmac == sw_hmac[..]);
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p: embassy_stm32::Peripherals = init();
+    let mut hw_hasher = Hash::new_blocking(p.HASH, Irqs);
+
+    test_interrupt(&mut hw_hasher);
+    // Run it a second time to check hash-after-hmac
+    test_interrupt(&mut hw_hasher);
 
     info!("Test OK");
     cortex_m::asm::bkpt();