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authorDario Nieuwenhuis <[email protected]>2023-06-19 22:39:08 +0200
committerDario Nieuwenhuis <[email protected]>2023-06-19 23:03:31 +0200
commit428a4ba3f98d81de28f8f72115ed6eff5401b46a (patch)
treeff6c3a571f64358b6a9046584fa65acc50dec104
parent990dd5e5db7134193259fcf350c0928b9a64df97 (diff)
stm32/gpdma: clear all interrupts after reset.
Reset doesn't clear them, this causes subsequent transfers to instantly complete because the TC flag was set from before.
-rw-r--r--embassy-stm32/src/dma/gpdma.rs1
1 files changed, 1 insertions, 0 deletions
diff --git a/embassy-stm32/src/dma/gpdma.rs b/embassy-stm32/src/dma/gpdma.rs
index c600df92d..b7bcf7795 100644
--- a/embassy-stm32/src/dma/gpdma.rs
+++ b/embassy-stm32/src/dma/gpdma.rs
@@ -252,6 +252,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
252 super::dmamux::configure_dmamux(&mut *this.channel, request); 252 super::dmamux::configure_dmamux(&mut *this.channel, request);
253 253
254 ch.cr().write(|w| w.set_reset(true)); 254 ch.cr().write(|w| w.set_reset(true));
255 ch.fcr().write(|w| w.0 = 0xFFFF_FFFF); // clear all irqs
255 ch.llr().write(|_| {}); // no linked list 256 ch.llr().write(|_| {}); // no linked list
256 ch.tr1().write(|w| { 257 ch.tr1().write(|w| {
257 w.set_sdw(data_size.into()); 258 w.set_sdw(data_size.into());