diff options
| author | Timo Kröger <[email protected]> | 2021-07-22 14:52:16 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2021-07-24 09:26:07 +0200 |
| commit | 43c4f242070ff1d239504c9e01d53c94390e62b7 (patch) | |
| tree | f9a513fa5d6e562a29f8caf268637753aaea90d3 | |
| parent | 5a4a5ce33417f66cb64713a8f97d7897c024f15f (diff) | |
STM32 BDMA: Use interrupt flags instead of atomics
| -rw-r--r-- | embassy-stm32/src/dma/bdma.rs | 52 |
1 files changed, 22 insertions, 30 deletions
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs index adb288eb0..99ade03c0 100644 --- a/embassy-stm32/src/dma/bdma.rs +++ b/embassy-stm32/src/dma/bdma.rs | |||
| @@ -3,7 +3,6 @@ | |||
| 3 | use core::future::Future; | 3 | use core::future::Future; |
| 4 | use core::task::Poll; | 4 | use core::task::Poll; |
| 5 | 5 | ||
| 6 | use atomic_polyfill::{AtomicU8, Ordering}; | ||
| 7 | use embassy::interrupt::{Interrupt, InterruptExt}; | 6 | use embassy::interrupt::{Interrupt, InterruptExt}; |
| 8 | use embassy::util::{AtomicWaker, OnDrop}; | 7 | use embassy::util::{AtomicWaker, OnDrop}; |
| 9 | use futures::future::poll_fn; | 8 | use futures::future::poll_fn; |
| @@ -15,22 +14,16 @@ use crate::pac::bdma::vals; | |||
| 15 | use crate::rcc::sealed::RccPeripheral; | 14 | use crate::rcc::sealed::RccPeripheral; |
| 16 | 15 | ||
| 17 | const CH_COUNT: usize = pac::peripheral_count!(bdma) * 8; | 16 | const CH_COUNT: usize = pac::peripheral_count!(bdma) * 8; |
| 18 | const CH_STATUS_NONE: u8 = 0; | ||
| 19 | const CH_STATUS_COMPLETED: u8 = 1; | ||
| 20 | const CH_STATUS_ERROR: u8 = 2; | ||
| 21 | 17 | ||
| 22 | struct State { | 18 | struct State { |
| 23 | ch_wakers: [AtomicWaker; CH_COUNT], | 19 | ch_wakers: [AtomicWaker; CH_COUNT], |
| 24 | ch_status: [AtomicU8; CH_COUNT], | ||
| 25 | } | 20 | } |
| 26 | 21 | ||
| 27 | impl State { | 22 | impl State { |
| 28 | const fn new() -> Self { | 23 | const fn new() -> Self { |
| 29 | const AW: AtomicWaker = AtomicWaker::new(); | 24 | const AW: AtomicWaker = AtomicWaker::new(); |
| 30 | const AU: AtomicU8 = AtomicU8::new(CH_STATUS_NONE); | ||
| 31 | Self { | 25 | Self { |
| 32 | ch_wakers: [AW; CH_COUNT], | 26 | ch_wakers: [AW; CH_COUNT], |
| 33 | ch_status: [AU; CH_COUNT], | ||
| 34 | } | 27 | } |
| 35 | } | 28 | } |
| 36 | } | 29 | } |
| @@ -57,21 +50,17 @@ pub(crate) unsafe fn do_transfer( | |||
| 57 | let ch = dma.ch(channel_number as _); | 50 | let ch = dma.ch(channel_number as _); |
| 58 | 51 | ||
| 59 | // Reset status | 52 | // Reset status |
| 60 | // Generate a DMB here to flush the store buffer (M7) before enabling the DMA | 53 | dma.ifcr().write(|w| { |
| 61 | STATE.ch_status[state_number as usize].store(CH_STATUS_NONE, Ordering::Release); | 54 | w.set_tcif(channel_number as _, true); |
| 55 | w.set_teif(channel_number as _, true); | ||
| 56 | }); | ||
| 62 | 57 | ||
| 63 | let on_drop = OnDrop::new(move || unsafe { | 58 | let on_drop = OnDrop::new(move || unsafe { |
| 64 | ch.cr().modify(|w| { | 59 | // Disable the channel and interrupts with the default value. |
| 65 | w.set_tcie(false); | 60 | ch.cr().write(|_| ()); |
| 66 | w.set_teie(false); | ||
| 67 | w.set_en(false); | ||
| 68 | }); | ||
| 69 | while ch.cr().read().en() {} | ||
| 70 | 61 | ||
| 71 | // Disabling the DMA mid transfer might cause some flags to be set, clear them all for the | 62 | // Wait for the transfer to complete when it was ongoing. |
| 72 | // next transfer | 63 | while ch.cr().read().en() {} |
| 73 | dma.ifcr() | ||
| 74 | .write(|w| w.set_gif(channel_number as usize, true)); | ||
| 75 | }); | 64 | }); |
| 76 | 65 | ||
| 77 | #[cfg(dmamux)] | 66 | #[cfg(dmamux)] |
| @@ -103,15 +92,20 @@ pub(crate) unsafe fn do_transfer( | |||
| 103 | async move { | 92 | async move { |
| 104 | let res = poll_fn(|cx| { | 93 | let res = poll_fn(|cx| { |
| 105 | STATE.ch_wakers[state_number as usize].register(cx.waker()); | 94 | STATE.ch_wakers[state_number as usize].register(cx.waker()); |
| 106 | match STATE.ch_status[state_number as usize].load(Ordering::Acquire) { | 95 | |
| 107 | CH_STATUS_NONE => Poll::Pending, | 96 | let isr = dma.isr().read(); |
| 108 | x => Poll::Ready(x), | 97 | |
| 98 | // TODO handle error | ||
| 99 | assert!(!isr.teif(channel_number as _)); | ||
| 100 | |||
| 101 | if isr.tcif(channel_number as _) { | ||
| 102 | Poll::Ready(()) | ||
| 103 | } else { | ||
| 104 | Poll::Pending | ||
| 109 | } | 105 | } |
| 110 | }) | 106 | }) |
| 111 | .await; | 107 | .await; |
| 112 | 108 | ||
| 113 | // TODO handle error | ||
| 114 | assert!(res == CH_STATUS_COMPLETED); | ||
| 115 | drop(on_drop) | 109 | drop(on_drop) |
| 116 | } | 110 | } |
| 117 | } | 111 | } |
| @@ -136,12 +130,10 @@ unsafe fn on_irq() { | |||
| 136 | let dman = dma_num!($dma); | 130 | let dman = dma_num!($dma); |
| 137 | 131 | ||
| 138 | for chn in 0..crate::pac::dma_channels_count!($dma) { | 132 | for chn in 0..crate::pac::dma_channels_count!($dma) { |
| 139 | let n = dman * 8 + chn; | 133 | let cr = pac::$dma.ch(chn).cr(); |
| 140 | if isr.teif(chn) { | 134 | if isr.tcif(chn) && cr.read().tcie() { |
| 141 | STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed); | 135 | cr.write(|_| ()); // Disable channel interrupts with the default value. |
| 142 | STATE.ch_wakers[n].wake(); | 136 | let n = dma_num!($dma) * 8 + chn; |
| 143 | } else if isr.tcif(chn) { | ||
| 144 | STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed); | ||
| 145 | STATE.ch_wakers[n].wake(); | 137 | STATE.ch_wakers[n].wake(); |
| 146 | } | 138 | } |
| 147 | } | 139 | } |
