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authorDario Nieuwenhuis <[email protected]>2023-11-26 23:42:03 +0000
committerGitHub <[email protected]>2023-11-26 23:42:03 +0000
commit44816313268ec2c8b0e8a11443836db48731edc7 (patch)
tree9108acd48114f197b39e126c29c507436f618a5d
parentff3baf1e90b3b87c203eb64dfe023843604e03c3 (diff)
parentcf13f70ea929ee550e418fe3c954b0415207ca88 (diff)
Merge pull request #2222 from embassy-rs/f446-hil
f446 hil
-rwxr-xr-xci.sh3
-rw-r--r--embassy-stm32/src/sdmmc/mod.rs8
-rw-r--r--tests/stm32/Cargo.toml23
-rw-r--r--tests/stm32/src/bin/can.rs12
-rw-r--r--tests/stm32/src/bin/dac.rs21
-rw-r--r--tests/stm32/src/bin/sdmmc.rs11
-rw-r--r--tests/stm32/src/common.rs35
7 files changed, 73 insertions, 40 deletions
diff --git a/ci.sh b/ci.sh
index aff88353c..5a4773da6 100755
--- a/ci.sh
+++ b/ci.sh
@@ -190,6 +190,7 @@ cargo batch \
190 --- build --release --manifest-path examples/wasm/Cargo.toml --target wasm32-unknown-unknown --out-dir out/examples/wasm \ 190 --- build --release --manifest-path examples/wasm/Cargo.toml --target wasm32-unknown-unknown --out-dir out/examples/wasm \
191 --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f103c8 --out-dir out/tests/stm32f103c8 \ 191 --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f103c8 --out-dir out/tests/stm32f103c8 \
192 --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f429zi --out-dir out/tests/stm32f429zi \ 192 --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f429zi --out-dir out/tests/stm32f429zi \
193 --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f446re --out-dir out/tests/stm32f446re \
193 --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32g491re --out-dir out/tests/stm32g491re \ 194 --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32g491re --out-dir out/tests/stm32g491re \
194 --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32g071rb --out-dir out/tests/stm32g071rb \ 195 --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32g071rb --out-dir out/tests/stm32g071rb \
195 --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32c031c6 --out-dir out/tests/stm32c031c6 \ 196 --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32c031c6 --out-dir out/tests/stm32c031c6 \
@@ -220,6 +221,8 @@ cargo batch \
220rm out/tests/stm32wb55rg/wpan_mac 221rm out/tests/stm32wb55rg/wpan_mac
221rm out/tests/stm32wb55rg/wpan_ble 222rm out/tests/stm32wb55rg/wpan_ble
222 223
224# not in CI yet.
225rm -rf out/tests/stm32f446re
223 226
224# unstable, I think it's running out of RAM? 227# unstable, I think it's running out of RAM?
225rm out/tests/stm32f207zg/eth 228rm out/tests/stm32f207zg/eth
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index a99a5707e..27a12062c 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -1457,8 +1457,8 @@ cfg_if::cfg_if! {
1457 macro_rules! kernel_clk { 1457 macro_rules! kernel_clk {
1458 ($inst:ident) => { 1458 ($inst:ident) => {
1459 critical_section::with(|_| unsafe { 1459 critical_section::with(|_| unsafe {
1460 crate::rcc::get_freqs().pll1_q 1460 unwrap!(crate::rcc::get_freqs().pll1_q)
1461 }).expect("PLL48 is required for SDIO") 1461 })
1462 } 1462 }
1463 } 1463 }
1464 } else if #[cfg(stm32f7)] { 1464 } else if #[cfg(stm32f7)] {
@@ -1469,7 +1469,7 @@ cfg_if::cfg_if! {
1469 if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS { 1469 if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS {
1470 crate::rcc::get_freqs().sys 1470 crate::rcc::get_freqs().sys
1471 } else { 1471 } else {
1472 crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC") 1472 unwrap!(crate::rcc::get_freqs().pll1_q)
1473 } 1473 }
1474 }) 1474 })
1475 }; 1475 };
@@ -1479,7 +1479,7 @@ cfg_if::cfg_if! {
1479 if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS { 1479 if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS {
1480 crate::rcc::get_freqs().sys 1480 crate::rcc::get_freqs().sys
1481 } else { 1481 } else {
1482 crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC") 1482 unwrap!(crate::rcc::get_freqs().pll1_q)
1483 } 1483 }
1484 }) 1484 })
1485 }; 1485 };
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index ab7016165..785082256 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -6,28 +6,29 @@ license = "MIT OR Apache-2.0"
6autobins = false 6autobins = false
7 7
8[features] 8[features]
9stm32c031c6 = ["embassy-stm32/stm32c031c6", "cm0", "not-gpdma"]
9stm32f103c8 = ["embassy-stm32/stm32f103c8", "not-gpdma"] 10stm32f103c8 = ["embassy-stm32/stm32f103c8", "not-gpdma"]
11stm32f207zg = ["embassy-stm32/stm32f207zg", "chrono", "not-gpdma", "eth", "rng"]
12stm32f303ze = ["embassy-stm32/stm32f303ze", "chrono", "not-gpdma"]
10stm32f429zi = ["embassy-stm32/stm32f429zi", "chrono", "eth", "stop", "can", "not-gpdma", "dac-adc-pin", "rng"] 13stm32f429zi = ["embassy-stm32/stm32f429zi", "chrono", "eth", "stop", "can", "not-gpdma", "dac-adc-pin", "rng"]
14stm32f446re = ["embassy-stm32/stm32f446re", "chrono", "stop", "can", "not-gpdma", "dac-adc-pin", "sdmmc"]
15stm32f767zi = ["embassy-stm32/stm32f767zi", "chrono", "not-gpdma", "eth", "rng"]
11stm32g071rb = ["embassy-stm32/stm32g071rb", "cm0", "not-gpdma", "dac-adc-pin"] 16stm32g071rb = ["embassy-stm32/stm32g071rb", "cm0", "not-gpdma", "dac-adc-pin"]
12stm32c031c6 = ["embassy-stm32/stm32c031c6", "cm0", "not-gpdma"]
13stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "stop", "not-gpdma", "rng"] 17stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "stop", "not-gpdma", "rng"]
14stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac-adc-pin", "rng"] 18stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng"]
15stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng"] 19stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng"]
20stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac-adc-pin", "rng"]
16stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng"] 21stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng"]
17stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng"]
18stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng"]
19stm32u585ai = ["embassy-stm32/stm32u585ai", "chrono", "rng"]
20stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng"]
21stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng"]
22stm32l073rz = ["embassy-stm32/stm32l073rz", "cm0", "not-gpdma", "rng"] 22stm32l073rz = ["embassy-stm32/stm32l073rz", "cm0", "not-gpdma", "rng"]
23stm32l152re = ["embassy-stm32/stm32l152re", "chrono", "not-gpdma"] 23stm32l152re = ["embassy-stm32/stm32l152re", "chrono", "not-gpdma"]
24stm32l496zg = ["embassy-stm32/stm32l496zg", "not-gpdma", "rng"]
24stm32l4a6zg = ["embassy-stm32/stm32l4a6zg", "chrono", "not-gpdma", "rng"] 25stm32l4a6zg = ["embassy-stm32/stm32l4a6zg", "chrono", "not-gpdma", "rng"]
25stm32l4r5zi = ["embassy-stm32/stm32l4r5zi", "chrono", "not-gpdma", "rng"] 26stm32l4r5zi = ["embassy-stm32/stm32l4r5zi", "chrono", "not-gpdma", "rng"]
26stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma", "rng"] 27stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma", "rng"]
27stm32f767zi = ["embassy-stm32/stm32f767zi", "chrono", "not-gpdma", "eth", "rng"] 28stm32u585ai = ["embassy-stm32/stm32u585ai", "chrono", "rng"]
28stm32f207zg = ["embassy-stm32/stm32f207zg", "chrono", "not-gpdma", "eth", "rng"] 29stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng"]
29stm32f303ze = ["embassy-stm32/stm32f303ze", "chrono", "not-gpdma"] 30stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng"]
30stm32l496zg = ["embassy-stm32/stm32l496zg", "not-gpdma", "rng"] 31stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng"]
31stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"] 32stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"]
32 33
33eth = [] 34eth = []
diff --git a/tests/stm32/src/bin/can.rs b/tests/stm32/src/bin/can.rs
index acf545216..8d782d2e7 100644
--- a/tests/stm32/src/bin/can.rs
+++ b/tests/stm32/src/bin/can.rs
@@ -27,21 +27,21 @@ bind_interrupts!(struct Irqs {
27 27
28#[embassy_executor::main] 28#[embassy_executor::main]
29async fn main(_spawner: Spawner) { 29async fn main(_spawner: Spawner) {
30 let mut p = embassy_stm32::init(config()); 30 let p = embassy_stm32::init(config());
31 info!("Hello World!"); 31 info!("Hello World!");
32 32
33 // HW is connected as follows: 33 let can = peri!(p, CAN);
34 // PB13 -> PD0 34 let tx = peri!(p, CAN_TX);
35 // PB12 -> PD1 35 let mut rx = peri!(p, CAN_RX);
36 36
37 // The next two lines are a workaround for testing without transceiver. 37 // The next two lines are a workaround for testing without transceiver.
38 // To synchronise to the bus the RX input needs to see a high level. 38 // To synchronise to the bus the RX input needs to see a high level.
39 // Use `mem::forget()` to release the borrow on the pin but keep the 39 // Use `mem::forget()` to release the borrow on the pin but keep the
40 // pull-up resistor enabled. 40 // pull-up resistor enabled.
41 let rx_pin = Input::new(&mut p.PD0, Pull::Up); 41 let rx_pin = Input::new(&mut rx, Pull::Up);
42 core::mem::forget(rx_pin); 42 core::mem::forget(rx_pin);
43 43
44 let mut can = Can::new(p.CAN1, p.PD0, p.PD1, Irqs); 44 let mut can = Can::new(can, rx, tx, Irqs);
45 45
46 info!("Configuring can..."); 46 info!("Configuring can...");
47 47
diff --git a/tests/stm32/src/bin/dac.rs b/tests/stm32/src/bin/dac.rs
index 824eb8803..29d5f866f 100644
--- a/tests/stm32/src/bin/dac.rs
+++ b/tests/stm32/src/bin/dac.rs
@@ -6,6 +6,8 @@
6 6
7#[path = "../common.rs"] 7#[path = "../common.rs"]
8mod common; 8mod common;
9use core::f32::consts::PI;
10
9use common::*; 11use common::*;
10use defmt::assert; 12use defmt::assert;
11use embassy_executor::Spawner; 13use embassy_executor::Spawner;
@@ -13,6 +15,7 @@ use embassy_stm32::adc::Adc;
13use embassy_stm32::dac::{DacCh1, Value}; 15use embassy_stm32::dac::{DacCh1, Value};
14use embassy_stm32::dma::NoDma; 16use embassy_stm32::dma::NoDma;
15use embassy_time::{Delay, Timer}; 17use embassy_time::{Delay, Timer};
18use micromath::F32Ext;
16use {defmt_rtt as _, panic_probe as _}; 19use {defmt_rtt as _, panic_probe as _};
17 20
18#[embassy_executor::main] 21#[embassy_executor::main]
@@ -20,24 +23,22 @@ async fn main(_spawner: Spawner) {
20 // Initialize the board and obtain a Peripherals instance 23 // Initialize the board and obtain a Peripherals instance
21 let p: embassy_stm32::Peripherals = embassy_stm32::init(config()); 24 let p: embassy_stm32::Peripherals = embassy_stm32::init(config());
22 25
23 #[cfg(feature = "stm32f429zi")] 26 let dac = peri!(p, DAC);
24 let dac_peripheral = p.DAC; 27 let dac_pin = peri!(p, DAC_PIN);
25 28 let mut adc_pin = unsafe { core::ptr::read(&dac_pin) };
26 #[cfg(any(feature = "stm32h755zi", feature = "stm32g071rb"))]
27 let dac_peripheral = p.DAC1;
28 29
29 let mut dac = DacCh1::new(dac_peripheral, NoDma, p.PA4); 30 let mut dac = DacCh1::new(dac, NoDma, dac_pin);
30 let mut adc = Adc::new(p.ADC1, &mut Delay); 31 let mut adc = Adc::new(p.ADC1, &mut Delay);
31 32
32 #[cfg(feature = "stm32h755zi")] 33 #[cfg(feature = "stm32h755zi")]
33 let normalization_factor = 256; 34 let normalization_factor = 256;
34 #[cfg(any(feature = "stm32f429zi", feature = "stm32g071rb"))] 35 #[cfg(any(feature = "stm32f429zi", feature = "stm32f446re", feature = "stm32g071rb"))]
35 let normalization_factor: i32 = 16; 36 let normalization_factor: i32 = 16;
36 37
37 dac.set(Value::Bit8(0)); 38 dac.set(Value::Bit8(0));
38 // Now wait a little to obtain a stable value 39 // Now wait a little to obtain a stable value
39 Timer::after_millis(30).await; 40 Timer::after_millis(30).await;
40 let offset = adc.read(&mut unsafe { embassy_stm32::Peripherals::steal() }.PA4); 41 let offset = adc.read(&mut adc_pin);
41 42
42 for v in 0..=255 { 43 for v in 0..=255 {
43 // First set the DAC output value 44 // First set the DAC output value
@@ -62,10 +63,6 @@ async fn main(_spawner: Spawner) {
62 cortex_m::asm::bkpt(); 63 cortex_m::asm::bkpt();
63} 64}
64 65
65use core::f32::consts::PI;
66
67use micromath::F32Ext;
68
69fn to_sine_wave(v: u8) -> u8 { 66fn to_sine_wave(v: u8) -> u8 {
70 if v >= 128 { 67 if v >= 128 {
71 // top half 68 // top half
diff --git a/tests/stm32/src/bin/sdmmc.rs b/tests/stm32/src/bin/sdmmc.rs
index 515025386..341d34bad 100644
--- a/tests/stm32/src/bin/sdmmc.rs
+++ b/tests/stm32/src/bin/sdmmc.rs
@@ -5,11 +5,12 @@
5#[path = "../common.rs"] 5#[path = "../common.rs"]
6mod common; 6mod common;
7 7
8use defmt::{assert_eq, *}; 8use common::*;
9use defmt::assert_eq;
9use embassy_executor::Spawner; 10use embassy_executor::Spawner;
10use embassy_stm32::sdmmc::{DataBlock, Sdmmc}; 11use embassy_stm32::sdmmc::{DataBlock, Sdmmc};
11use embassy_stm32::time::mhz; 12use embassy_stm32::time::mhz;
12use embassy_stm32::{bind_interrupts, peripherals, sdmmc, Config}; 13use embassy_stm32::{bind_interrupts, peripherals, sdmmc};
13use {defmt_rtt as _, panic_probe as _}; 14use {defmt_rtt as _, panic_probe as _};
14 15
15bind_interrupts!(struct Irqs { 16bind_interrupts!(struct Irqs {
@@ -20,12 +21,8 @@ bind_interrupts!(struct Irqs {
20async fn main(_spawner: Spawner) { 21async fn main(_spawner: Spawner) {
21 info!("Hello World!"); 22 info!("Hello World!");
22 23
23 let mut config = Config::default(); 24 let p = embassy_stm32::init(config());
24 config.rcc.sys_ck = Some(mhz(48));
25 config.rcc.pll48 = true;
26 let p = embassy_stm32::init(config);
27 25
28 #[cfg(feature = "stm32f429zi")]
29 let (mut sdmmc, mut dma, mut clk, mut cmd, mut d0, mut d1, mut d2, mut d3) = 26 let (mut sdmmc, mut dma, mut clk, mut cmd, mut d0, mut d1, mut d2, mut d3) =
30 (p.SDIO, p.DMA2_CH3, p.PC12, p.PD2, p.PC8, p.PC9, p.PC10, p.PC11); 27 (p.SDIO, p.DMA2_CH3, p.PC12, p.PD2, p.PC8, p.PC9, p.PC10, p.PC11);
31 28
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index a44e8230f..155e1d9df 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -14,6 +14,8 @@ teleprobe_meta::target!(b"nucleo-stm32g491re");
14teleprobe_meta::target!(b"nucleo-stm32g071rb"); 14teleprobe_meta::target!(b"nucleo-stm32g071rb");
15#[cfg(feature = "stm32f429zi")] 15#[cfg(feature = "stm32f429zi")]
16teleprobe_meta::target!(b"nucleo-stm32f429zi"); 16teleprobe_meta::target!(b"nucleo-stm32f429zi");
17#[cfg(feature = "stm32f446re")]
18teleprobe_meta::target!(b"weact-stm32f446re");
17#[cfg(feature = "stm32wb55rg")] 19#[cfg(feature = "stm32wb55rg")]
18teleprobe_meta::target!(b"nucleo-stm32wb55rg"); 20teleprobe_meta::target!(b"nucleo-stm32wb55rg");
19#[cfg(feature = "stm32h755zi")] 21#[cfg(feature = "stm32h755zi")]
@@ -99,14 +101,25 @@ define_peris!(
99define_peris!( 101define_peris!(
100 UART = USART1, UART_TX = PC4, UART_RX = PC5, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2, 102 UART = USART1, UART_TX = PC4, UART_RX = PC5, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
101 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2, 103 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
104 DAC = DAC1, DAC_PIN = PA4,
102 @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;}, 105 @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
103); 106);
104#[cfg(feature = "stm32f429zi")] 107#[cfg(feature = "stm32f429zi")]
105define_peris!( 108define_peris!(
106 UART = USART6, UART_TX = PG14, UART_RX = PG9, UART_TX_DMA = DMA2_CH6, UART_RX_DMA = DMA2_CH1, 109 UART = USART6, UART_TX = PG14, UART_RX = PG9, UART_TX_DMA = DMA2_CH6, UART_RX_DMA = DMA2_CH1,
107 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA2_CH3, SPI_RX_DMA = DMA2_CH2, 110 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA2_CH3, SPI_RX_DMA = DMA2_CH2,
111 DAC = DAC, DAC_PIN = PA4,
112 CAN = CAN1, CAN_RX = PD0, CAN_TX = PD1,
108 @irq UART = {USART6 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART6>;}, 113 @irq UART = {USART6 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART6>;},
109); 114);
115#[cfg(feature = "stm32f446re")]
116define_peris!(
117 UART = USART1, UART_TX = PA9, UART_RX = PA10, UART_TX_DMA = DMA2_CH7, UART_RX_DMA = DMA2_CH5,
118 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA2_CH3, SPI_RX_DMA = DMA2_CH2,
119 DAC = DAC, DAC_PIN = PA4,
120 CAN = CAN1, CAN_RX = PA11, CAN_TX = PA12,
121 @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
122);
110#[cfg(feature = "stm32wb55rg")] 123#[cfg(feature = "stm32wb55rg")]
111define_peris!( 124define_peris!(
112 UART = LPUART1, UART_TX = PA2, UART_RX = PA3, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2, 125 UART = LPUART1, UART_TX = PA2, UART_RX = PA3, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
@@ -117,6 +130,7 @@ define_peris!(
117define_peris!( 130define_peris!(
118 UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1, 131 UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1,
119 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PB5, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1, 132 SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PB5, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1,
133 DAC = DAC1, DAC_PIN = PA4,
120 @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;}, 134 @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
121); 135);
122#[cfg(feature = "stm32h7a3zi")] 136#[cfg(feature = "stm32h7a3zi")]
@@ -282,6 +296,27 @@ pub fn config() -> Config {
282 config.rcc.sys = Sysclk::PLL1_P; 296 config.rcc.sys = Sysclk::PLL1_P;
283 } 297 }
284 298
299 #[cfg(feature = "stm32f446re")]
300 {
301 use embassy_stm32::rcc::*;
302 config.rcc.hse = Some(Hse {
303 freq: Hertz(8_000_000),
304 mode: HseMode::Oscillator,
305 });
306 config.rcc.pll_src = PllSource::HSE;
307 config.rcc.pll = Some(Pll {
308 prediv: PllPreDiv::DIV4,
309 mul: PllMul::MUL168,
310 divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168 Mhz.
311 divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48 Mhz.
312 divr: None,
313 });
314 config.rcc.ahb_pre = AHBPrescaler::DIV1;
315 config.rcc.apb1_pre = APBPrescaler::DIV4;
316 config.rcc.apb2_pre = APBPrescaler::DIV2;
317 config.rcc.sys = Sysclk::PLL1_P;
318 }
319
285 #[cfg(feature = "stm32f767zi")] 320 #[cfg(feature = "stm32f767zi")]
286 { 321 {
287 use embassy_stm32::rcc::*; 322 use embassy_stm32::rcc::*;