Merge branch 'main' of https://github.com/embassy-rs/embassy into lp-dma

14 files changed, 1018 insertions, 41 deletions

diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
index 6e1381925..da2ea5c79 100644
--- a/embassy-stm32/CHANGELOG.md
+++ b/embassy-stm32/CHANGELOG.md
@@ -75,6 +75,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - fix: fixing channel numbers on vbat and vddcore for adc on adc
 - adc: adding disable to vbat
 - feat: stm32/flash: add async support for h7 family
+- feat: stm32/lcd: added implementation
 
 ## 0.4.0 - 2025-08-26
 
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 2f4f2ce51..fbd00895d 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -200,11 +200,11 @@ aligned = "0.4.1"
 heapless = "0.9.1"
 
 #stm32-metapac = { version = "18" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-b77c8d968f53b18d6bdcd052e354b5070ec2bbc2" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-61abfb115273dc66ed99bf14545779a2aa0722c8" }
 
 [build-dependencies]
 #stm32-metapac = { version = "18", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-b77c8d968f53b18d6bdcd052e354b5070ec2bbc2", default-features = false, features = ["metadata"] }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-61abfb115273dc66ed99bf14545779a2aa0722c8", default-features = false, features = ["metadata"] }
 
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 3277ba440..e218e2492 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -1352,6 +1352,9 @@ fn main() {
         (("tsc", "G8_IO2"), quote!(crate::tsc::G8IO2Pin)),
         (("tsc", "G8_IO3"), quote!(crate::tsc::G8IO3Pin)),
         (("tsc", "G8_IO4"), quote!(crate::tsc::G8IO4Pin)),
+        (("lcd", "SEG"), quote!(crate::lcd::SegPin)),
+        (("lcd", "COM"), quote!(crate::lcd::ComPin)),
+        (("lcd", "VLCD"), quote!(crate::lcd::VlcdPin)),
         (("dac", "OUT1"), quote!(crate::dac::DacPin<Ch1>)),
         (("dac", "OUT2"), quote!(crate::dac::DacPin<Ch2>)),
     ].into();
@@ -1359,9 +1362,22 @@ fn main() {
     for p in METADATA.peripherals {
         if let Some(regs) = &p.registers {
             let mut adc_pairs: BTreeMap<u8, (Option<Ident>, Option<Ident>)> = BTreeMap::new();
+            let mut seen_lcd_seg_pins = HashSet::new();
 
             for pin in p.pins {
-                let key = (regs.kind, pin.signal);
+                let mut key = (regs.kind, pin.signal);
+
+                // LCD is special. There are so many pins!
+                if regs.kind == "lcd" {
+                    key.1 = pin.signal.trim_end_matches(char::is_numeric);
+
+                    if key.1 == "SEG" && !seen_lcd_seg_pins.insert(pin.pin) {
+                        // LCD has SEG pins multiplexed in the peripheral
+                        // This means we can see them twice. We need to skip those so we're not impl'ing the trait twice
+                        continue;
+                    }
+                }
+
                 if let Some(tr) = signals.get(&key) {
                     let mut peri = format_ident!("{}", p.name);
 
diff --git a/embassy-stm32/src/adc/adc4.rs b/embassy-stm32/src/adc/adc4.rs
index 472eb46fd..453513309 100644
--- a/embassy-stm32/src/adc/adc4.rs
+++ b/embassy-stm32/src/adc/adc4.rs
@@ -113,26 +113,11 @@ foreach_adc!(
             }
 
             fn enable() {
-                let cr_initial = ADC4::regs().cr().read();
-                let isr_initial = ADC4::regs().isr().read();
-
-                if cr_initial.aden() && isr_initial.adrdy() {
-                    return;
-                }
-
-                if cr_initial.aden() || cr_initial.adstart() {
-                    if cr_initial.adstart() {
-                        ADC4::regs().cr().modify(|w| w.set_adstp(true));
-                        while ADC4::regs().cr().read().adstart() {}
-                    }
-
-                    ADC4::regs().cr().modify(|w| w.set_addis(true));
-                    while ADC4::regs().cr().read().aden() {}
+                if !ADC4::regs().cr().read().aden()  || !ADC4::regs().isr().read().adrdy() {
+                    ADC4::regs().isr().write(|w| w.set_adrdy(true));
+                    ADC4::regs().cr().modify(|w| w.set_aden(true));
+                    while !ADC4::regs().isr().read().adrdy() {}
                 }
-
-                ADC4::regs().isr().write(|w| w.set_adrdy(true));
-                ADC4::regs().cr().modify(|w| w.set_aden(true));
-                while !ADC4::regs().isr().read().adrdy() {}
             }
 
             fn start() {
@@ -143,13 +128,17 @@ foreach_adc!(
             }
 
             fn stop() {
-                if ADC4::regs().cr().read().adstart() && !ADC4::regs().cr().read().addis() {
-                    ADC4::regs().cr().modify(|reg| {
-                        reg.set_adstp(true);
-                    });
+                let cr = ADC4::regs().cr().read();
+                if cr.adstart() {
+                    ADC4::regs().cr().modify(|w| w.set_adstp(true));
                     while ADC4::regs().cr().read().adstart() {}
                 }
 
+                if cr.aden() || cr.adstart() {
+                    ADC4::regs().cr().modify(|w| w.set_addis(true));
+                    while ADC4::regs().cr().read().aden() {}
+                }
+
                 // Reset configuration.
                 ADC4::regs().cfgr1().modify(|reg| {
                     reg.set_dmaen(false);
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 755cb78c2..6d53d9b91 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -192,6 +192,8 @@ impl<'d, T: AnyInstance> Adc<'d, T> {
         #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
         channel.setup();
 
+        // Ensure no conversions are ongoing
+        T::stop();
         #[cfg(any(adc_v2, adc_v3, adc_g0, adc_h7rs, adc_u0, adc_u5, adc_wba, adc_c0))]
         T::enable();
         T::configure_sequence([((channel.channel(), channel.is_differential()), sample_time)].into_iter());
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index 341b15674..3c4431ae0 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -79,12 +79,17 @@ impl<T: Instance> super::SealedAnyInstance for T {
         T::regs().dr().as_ptr() as *mut u16
     }
 
-    fn enable() {}
+    fn enable() {
+        T::regs().cr2().modify(|reg| {
+            reg.set_adon(true);
+        });
+
+        blocking_delay_us(3);
+    }
 
     fn start() {
         // Begin ADC conversions
         T::regs().cr2().modify(|reg| {
-            reg.set_adon(true);
             reg.set_swstart(true);
         });
     }
@@ -198,7 +203,7 @@ impl<T: Instance> super::SealedAnyInstance for T {
 
 impl<'d, T> Adc<'d, T>
 where
-    T: Instance,
+    T: Instance + super::AnyInstance,
 {
     pub fn new(adc: Peri<'d, T>) -> Self {
         Self::new_with_config(adc, Default::default())
@@ -209,11 +214,7 @@ where
 
         let presc = from_pclk2(T::frequency());
         T::common_regs().ccr().modify(|w| w.set_adcpre(presc));
-        T::regs().cr2().modify(|reg| {
-            reg.set_adon(true);
-        });
-
-        blocking_delay_us(3);
+        T::enable();
 
         if let Some(resolution) = config.resolution {
             T::regs().cr1().modify(|reg| reg.set_res(resolution.into()));
diff --git a/embassy-stm32/src/lcd.rs b/embassy-stm32/src/lcd.rs
new file mode 100644
index 000000000..ea29f1398
--- /dev/null
+++ b/embassy-stm32/src/lcd.rs
@@ -0,0 +1,510 @@
+//! LCD
+use core::marker::PhantomData;
+
+use embassy_hal_internal::{Peri, PeripheralType};
+
+use crate::gpio::{AfType, AnyPin, SealedPin};
+use crate::peripherals;
+use crate::rcc::{self, RccPeripheral};
+use crate::time::Hertz;
+
+#[cfg(any(stm32u0, stm32l073, stm32l083))]
+const NUM_SEGMENTS: u8 = 52;
+#[cfg(any(stm32wb, stm32l4x6, stm32l15x, stm32l162, stm32l4x3, stm32l4x6))]
+const NUM_SEGMENTS: u8 = 44;
+#[cfg(any(stm32l053, stm32l063, stm32l100))]
+const NUM_SEGMENTS: u8 = 32;
+
+/// LCD configuration struct
+#[non_exhaustive]
+#[derive(Debug, Clone, Copy)]
+pub struct Config {
+    #[cfg(lcd_v2)]
+    /// Enable the voltage output buffer for higher driving capability.
+    ///
+    /// The LCD driving capability is improved as buffers prevent the LCD capacitive loads from loading the resistor
+    /// bridge unacceptably and interfering with its voltage generation.
+    pub use_voltage_output_buffer: bool,
+    /// Enable SEG pin remapping. SEG[31:28] multiplexed with SEG[43:40]
+    pub use_segment_muxing: bool,
+    /// Bias selector
+    pub bias: Bias,
+    /// Duty selector
+    pub duty: Duty,
+    /// Internal or external voltage source
+    pub voltage_source: VoltageSource,
+    /// The frequency used to update the LCD with.
+    /// Should be between ~30 and ~100. Lower is better for power consumption, but has lower visual fidelity.
+    pub target_fps: Hertz,
+    /// LCD driver selector
+    pub drive: Drive,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            #[cfg(lcd_v2)]
+            use_voltage_output_buffer: false,
+            use_segment_muxing: false,
+            bias: Default::default(),
+            duty: Default::default(),
+            voltage_source: Default::default(),
+            target_fps: Hertz(60),
+            drive: Drive::Medium,
+        }
+    }
+}
+
+/// The number of voltage levels used when driving an LCD.
+/// Your LCD datasheet should tell you what to use.
+#[repr(u8)]
+#[derive(Debug, Default, Clone, Copy)]
+pub enum Bias {
+    /// 1/4 bias
+    #[default]
+    Quarter = 0b00,
+    /// 1/2 bias
+    Half = 0b01,
+    /// 1/3 bias
+    Third = 0b10,
+}
+
+/// The duty used by the LCD driver.
+///
+/// This is essentially how many COM pins you're using.
+#[repr(u8)]
+#[derive(Debug, Default, Clone, Copy)]
+pub enum Duty {
+    #[default]
+    /// Use a single COM pin
+    Static = 0b000,
+    /// Use two COM pins
+    Half = 0b001,
+    /// Use three COM pins
+    Third = 0b010,
+    /// Use four COM pins
+    Quarter = 0b011,
+    /// Use eight COM pins.
+    ///
+    /// In this mode, `COM[7:4]` outputs are available on `SEG[51:48]`.
+    /// This allows reducing the number of available segments.
+    Eigth = 0b100,
+}
+
+impl Duty {
+    fn num_com_pins(&self) -> u8 {
+        match self {
+            Duty::Static => 1,
+            Duty::Half => 2,
+            Duty::Third => 3,
+            Duty::Quarter => 4,
+            Duty::Eigth => 8,
+        }
+    }
+}
+
+/// Whether to use the internal or external voltage source to drive the LCD
+#[repr(u8)]
+#[derive(Debug, Default, Clone, Copy)]
+pub enum VoltageSource {
+    #[default]
+    /// Voltage stepup converter
+    Internal,
+    /// VLCD pin
+    External,
+}
+
+/// Defines the pulse duration in terms of ck_ps pulses.
+///
+/// A short pulse leads to lower power consumption, but displays with high internal resistance
+/// may need a longer pulse to achieve satisfactory contrast.
+/// Note that the pulse is never longer than one half prescaled LCD clock period.
+///
+/// Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast.
+/// `PermanentHighDrive` is useful in this case if some additional power consumption can be tolerated.
+///
+/// Basically, for power usage, you want this as low as possible while still being able to use the LCD
+/// with a good enough contrast.
+#[repr(u8)]
+#[derive(Debug, Clone, Copy)]
+pub enum Drive {
+    /// Zero clock pulse on duration
+    Lowest = 0x00,
+    /// One clock pulse on duration
+    VeryLow = 0x01,
+    /// Two clock pulse on duration
+    Low = 0x02,
+    /// Three clock pulse on duration
+    Medium = 0x03,
+    /// Four clock pulse on duration
+    MediumHigh = 0x04,
+    /// Five clock pulse on duration
+    High = 0x05,
+    /// Six clock pulse on duration
+    VeryHigh = 0x06,
+    /// Seven clock pulse on duration
+    Highest = 0x07,
+    /// Enables the highdrive bit of the hardware
+    PermanentHighDrive = 0x09,
+}
+
+/// LCD driver.
+pub struct Lcd<'d, T: Instance> {
+    _peri: PhantomData<&'d mut T>,
+    duty: Duty,
+    ck_div: u32,
+}
+
+impl<'d, T: Instance> Lcd<'d, T> {
+    /// Initialize the lcd driver.
+    ///
+    /// The `pins` parameter must contain *all* segment and com pins that are connected to the LCD.
+    /// This is not further checked by this driver. Pins not routed to the LCD can be used for other purposes.
+    pub fn new<const N: usize>(
+        _peripheral: Peri<'d, T>,
+        config: Config,
+        vlcd_pin: Peri<'_, impl VlcdPin<T>>,
+        pins: [LcdPin<'d, T>; N],
+    ) -> Self {
+        rcc::enable_and_reset::<T>();
+
+        vlcd_pin.set_as_af(
+            vlcd_pin.af_num(),
+            AfType::output(crate::gpio::OutputType::PushPull, crate::gpio::Speed::VeryHigh),
+        );
+
+        assert_eq!(
+            pins.iter().filter(|pin| !pin.is_seg).count(),
+            config.duty.num_com_pins() as usize,
+            "The number of provided COM pins is not the same as the duty configures"
+        );
+
+        // Set the pins
+        for pin in pins {
+            pin.pin.set_as_af(
+                pin.af_num,
+                AfType::output(crate::gpio::OutputType::PushPull, crate::gpio::Speed::VeryHigh),
+            );
+        }
+
+        // Initialize the display ram to 0
+        for i in 0..8 {
+            T::regs().ram_com(i).low().write_value(0);
+            T::regs().ram_com(i).high().write_value(0);
+        }
+
+        // Calculate the clock dividers
+        let Some(lcd_clk) = (unsafe { rcc::get_freqs().rtc.to_hertz() }) else {
+            panic!("The LCD driver needs the RTC/LCD clock to be running");
+        };
+        let duty_divider = match config.duty {
+            Duty::Static => 1,
+            Duty::Half => 2,
+            Duty::Third => 3,
+            Duty::Quarter => 4,
+            Duty::Eigth => 8,
+        };
+        let target_clock = config.target_fps.0 * duty_divider;
+        let target_division = lcd_clk.0 / target_clock;
+
+        let mut ps = 0;
+        let mut div = 0;
+        let mut best_fps_match = u32::MAX;
+
+        for trial_div in 0..0xF {
+            let trial_ps = (target_division / (trial_div + 16))
+                .next_power_of_two()
+                .trailing_zeros();
+            let fps = lcd_clk.0 / ((1 << trial_ps) * (trial_div + 16)) / duty_divider;
+
+            if fps < config.target_fps.0 {
+                continue;
+            }
+
+            if fps < best_fps_match {
+                ps = trial_ps;
+                div = trial_div;
+                best_fps_match = fps;
+            }
+        }
+
+        let ck_div = lcd_clk.0 / ((1 << ps) * (div + 16));
+
+        trace!(
+            "lcd_clk: {}, fps: {}, ps: {}, div: {}, ck_div: {}",
+            lcd_clk, best_fps_match, ps, div, ck_div
+        );
+
+        if best_fps_match == u32::MAX || ps > 0xF {
+            panic!("Lcd clock error");
+        }
+
+        // Set the frame control
+        T::regs().fcr().modify(|w| {
+            w.set_ps(ps as u8);
+            w.set_div(div as u8);
+            w.set_cc(0b100); // Init in the middle-ish
+            w.set_dead(0b000);
+            w.set_pon(config.drive as u8 & 0x07);
+            w.set_hd((config.drive as u8 & !0x07) != 0);
+        });
+
+        // Wait for the frame control to synchronize
+        while !T::regs().sr().read().fcrsf() {}
+
+        // Set the control register values
+        T::regs().cr().modify(|w| {
+            #[cfg(lcd_v2)]
+            w.set_bufen(config.use_voltage_output_buffer);
+            w.set_mux_seg(config.use_segment_muxing);
+            w.set_bias(config.bias as u8);
+            w.set_duty(config.duty as u8);
+            w.set_vsel(matches!(config.voltage_source, VoltageSource::External));
+        });
+
+        // Enable the lcd
+        T::regs().cr().modify(|w| w.set_lcden(true));
+
+        // Wait for the lcd to be enabled
+        while !T::regs().sr().read().ens() {}
+
+        // Wait for the stepup converter to be ready
+        while !T::regs().sr().read().rdy() {}
+
+        Self {
+            _peri: PhantomData,
+            duty: config.duty,
+            ck_div,
+        }
+    }
+
+    /// Change the contrast by changing the voltage being used.
+    ///
+    /// This is from low at 0 to high at 7.
+    pub fn set_contrast_control(&mut self, value: u8) {
+        assert!((0..=7).contains(&value));
+        T::regs().fcr().modify(|w| w.set_cc(value));
+    }
+
+    /// Change the contrast by introducing a deadtime to the signals
+    /// where the voltages are held at 0V.
+    ///
+    /// This is from no dead time at 0 to high dead time at 7.
+    pub fn set_dead_time(&mut self, value: u8) {
+        assert!((0..=7).contains(&value));
+        T::regs()
+            .fcr()
+            .modify(|w: &mut stm32_metapac::lcd::regs::Fcr| w.set_dead(value));
+    }
+
+    /// Write data into the display RAM. This overwrites the data already in it for the specified com index.
+    ///
+    /// The `com_index` value determines which part of the RAM is written to.
+    /// The `segments` value is a bitmap where each bit represents whether a pixel is turned on or off.
+    ///
+    /// This function waits last update request to be finished, but does not submit the buffer to the LCD with a new request.
+    /// Submission has to be done manually using [Self::submit_frame].
+    pub fn write_com_segments(&mut self, com_index: u8, segments: u64) {
+        while T::regs().sr().read().udr() {}
+
+        assert!(
+            com_index < self.duty.num_com_pins(),
+            "Com index cannot be higher than number of configured com pins (through the Duty setting in the config)"
+        );
+
+        assert!(
+            segments.leading_zeros() >= 64 - self.num_segments() as u32,
+            "Invalid segment pixel set",
+        );
+
+        T::regs()
+            .ram_com(com_index as usize)
+            .low()
+            .write_value((segments & 0xFFFF_FFFF) as u32);
+        T::regs()
+            .ram_com(com_index as usize)
+            .high()
+            .write_value(((segments >> 32) & 0xFFFF_FFFF) as u32);
+    }
+
+    /// Read the data from the display RAM.
+    ///
+    /// The `com_index` value determines which part of the RAM is read from.
+    ///
+    /// This function waits for the last update request to be finished.
+    pub fn read_com_segments(&self, com_index: u8) -> u64 {
+        while T::regs().sr().read().udr() {}
+
+        assert!(
+            com_index < self.duty.num_com_pins(),
+            "Com index cannot be higher than number of configured com pins (through the Duty setting in the config)"
+        );
+
+        let low = T::regs().ram_com(com_index as usize).low().read();
+        let high = T::regs().ram_com(com_index as usize).high().read();
+
+        ((high as u64) << 32) | low as u64
+    }
+
+    /// Submit the current RAM data to the LCD.
+    ///
+    /// This function waits until the RAM is writable, but does not wait for the frame to be drawn.
+    pub fn submit_frame(&mut self) {
+        while T::regs().sr().read().udr() {}
+        // Clear the update done flag
+        T::regs().sr().write(|w| w.set_udd(true));
+        // Set the update request flag
+        T::regs().sr().write(|w| w.set_udr(true));
+    }
+
+    /// Get the number of segments that are supported on this LCD
+    pub fn num_segments(&self) -> u8 {
+        match self.duty {
+            Duty::Eigth => NUM_SEGMENTS - 4, // With 8 coms, 4 of the segment pins turn into com pins
+            _ => NUM_SEGMENTS,
+        }
+    }
+
+    /// Get the pixel mask for the current LCD setup.
+    /// This is a mask of all bits that are allowed to be set in the [Self::write_com_segments] function.
+    pub fn segment_pixel_mask(&self) -> u64 {
+        (1 << self.num_segments()) - 1
+    }
+
+    /// Get the number of COM pins that were configured through the Drive config
+    pub fn num_com_pins(&self) -> u8 {
+        self.duty.num_com_pins()
+    }
+
+    /// Set the blink behavior on some pixels.
+    ///
+    /// The blink frequency is an approximation. It's divided from the clock selected by the FPS.
+    /// Play with the FPS value if you want the blink frequency to be more accurate.
+    ///
+    /// If a blink frequency cannot be attained, this function will panic.
+    pub fn set_blink(&mut self, selector: BlinkSelector, freq: BlinkFreq) {
+        // Freq * 100 to be able to do integer math
+        let scaled_blink_freq = match freq {
+            BlinkFreq::Hz0_25 => 25,
+            BlinkFreq::Hz0_5 => 50,
+            BlinkFreq::Hz1 => 100,
+            BlinkFreq::Hz2 => 200,
+            BlinkFreq::Hz4 => 400,
+        };
+
+        let desired_divider = self.ck_div * 100 / scaled_blink_freq;
+        let target_divider = desired_divider.next_power_of_two();
+        let power_divisions = target_divider.trailing_zeros();
+
+        trace!(
+            "Setting LCD blink frequency -> desired_divider: {}, target_divider: {}",
+            desired_divider, target_divider
+        );
+
+        assert!(
+            (8..=1024).contains(&target_divider),
+            "LCD blink frequency cannot be attained"
+        );
+
+        T::regs().fcr().modify(|reg| {
+            reg.set_blinkf((power_divisions - 3) as u8);
+            reg.set_blink(selector as u8);
+        })
+    }
+}
+
+impl<'d, T: Instance> Drop for Lcd<'d, T> {
+    fn drop(&mut self) {
+        // Disable the lcd
+        T::regs().cr().modify(|w| w.set_lcden(false));
+        rcc::disable::<T>();
+    }
+}
+
+/// Blink frequency
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum BlinkFreq {
+    /// 0.25 hz
+    Hz0_25,
+    /// 0.5 hz
+    Hz0_5,
+    /// 1 hz
+    Hz1,
+    /// 2 hz
+    Hz2,
+    /// 4 hz
+    Hz4,
+}
+
+/// Blink pixel selector
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(u8)]
+pub enum BlinkSelector {
+    /// No pixels blink
+    None = 0b00,
+    /// The SEG0, COM0 pixel blinks if the pixel is set
+    Seg0Com0 = 0b01,
+    /// The SEG0 pixel of all COMs blinks if the pixel is set
+    Seg0ComAll = 0b10,
+    /// All pixels blink if the pixel is set
+    All = 0b11,
+}
+
+/// A type-erased pin that can be configured as an LCD pin.
+/// This is used for passing pins to the new function in the array.
+pub struct LcdPin<'d, T: Instance> {
+    pin: Peri<'d, AnyPin>,
+    af_num: u8,
+    is_seg: bool,
+    _phantom: PhantomData<T>,
+}
+
+impl<'d, T: Instance> LcdPin<'d, T> {
+    /// Construct an LCD pin from any pin that supports it
+    pub fn new_seg(pin: Peri<'d, impl SegPin<T>>) -> Self {
+        let af = pin.af_num();
+
+        Self {
+            pin: pin.into(),
+            af_num: af,
+            is_seg: true,
+            _phantom: PhantomData,
+        }
+    }
+
+    /// Construct an LCD pin from any pin that supports it
+    pub fn new_com(pin: Peri<'d, impl ComPin<T>>) -> Self {
+        let af = pin.af_num();
+
+        Self {
+            pin: pin.into(),
+            af_num: af,
+            is_seg: false,
+            _phantom: PhantomData,
+        }
+    }
+}
+
+trait SealedInstance: crate::rcc::SealedRccPeripheral + PeripheralType {
+    fn regs() -> crate::pac::lcd::Lcd;
+}
+
+/// DSI instance trait.
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + RccPeripheral + 'static {}
+
+pin_trait!(SegPin, Instance);
+pin_trait!(ComPin, Instance);
+pin_trait!(VlcdPin, Instance);
+
+foreach_peripheral!(
+    (lcd, $inst:ident) => {
+        impl crate::lcd::SealedInstance for peripherals::$inst {
+            fn regs() -> crate::pac::lcd::Lcd {
+                crate::pac::$inst
+            }
+        }
+
+        impl crate::lcd::Instance for peripherals::$inst {}
+    };
+);
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index ef6f1d6dc..9e6ba1f34 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -95,6 +95,8 @@ pub mod i2c;
 pub mod i2s;
 #[cfg(stm32wb)]
 pub mod ipcc;
+#[cfg(lcd)]
+pub mod lcd;
 #[cfg(feature = "low-power")]
 pub mod low_power;
 #[cfg(lptim)]
diff --git a/examples/stm32u0/.cargo/config.toml b/examples/stm32u0/.cargo/config.toml
index 688347084..e9212cacb 100644
--- a/examples/stm32u0/.cargo/config.toml
+++ b/examples/stm32u0/.cargo/config.toml
@@ -1,6 +1,6 @@
 [target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace stm32u083rctx with your chip as listed in `probe-rs chip list`
-runner = "probe-rs run --chip stm32u083rctx"
+# replace stm32u083mctx with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip stm32u083mctx"
 
 [build]
 target = "thumbv6m-none-eabi"
diff --git a/examples/stm32u0/Cargo.toml b/examples/stm32u0/Cargo.toml
index 9f5227e3f..8cc894cb3 100644
--- a/examples/stm32u0/Cargo.toml
+++ b/examples/stm32u0/Cargo.toml
@@ -6,8 +6,8 @@ license = "MIT OR Apache-2.0"
 publish = false
 
 [dependencies]
-# Change stm32u083rc to your chip name, if necessary.
-embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32u083rc", "memory-x", "unstable-pac", "exti", "chrono"]  }
+# Change stm32u083mc to your chip name, if necessary.
+embassy-stm32 = { version = "0.4.0", path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32u083mc", "memory-x", "unstable-pac", "exti", "chrono"]  }
 embassy-sync = { version = "0.7.2", path = "../../embassy-sync", features = ["defmt"] }
 embassy-executor = { version = "0.9.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt"] }
 embassy-time = { version = "0.5.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
@@ -19,9 +19,7 @@ defmt-rtt = "1.0.0"
 
 cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7.0"
-embedded-hal = "0.2.6"
 panic-probe = { version = "1.0.0", features = ["print-defmt"] }
-heapless = { version = "0.8", default-features = false }
 
 micromath = "2.0.0"
 chrono = { version = "0.4.38", default-features = false }
diff --git a/examples/stm32u0/src/bin/lcd.rs b/examples/stm32u0/src/bin/lcd.rs
new file mode 100644
index 000000000..2b34d4ef1
--- /dev/null
+++ b/examples/stm32u0/src/bin/lcd.rs
@@ -0,0 +1,412 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::lcd::{Bias, BlinkFreq, BlinkSelector, Config, Duty, Lcd, LcdPin};
+use embassy_stm32::peripherals::LCD;
+use embassy_stm32::time::Hertz;
+use embassy_time::Duration;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = embassy_stm32::Config::default();
+    // The RTC clock = the LCD clock and must be running
+    {
+        use embassy_stm32::rcc::*;
+        config.rcc.sys = Sysclk::PLL1_R;
+        config.rcc.hsi = true;
+        config.rcc.pll = Some(Pll {
+            source: PllSource::HSI, // 16 MHz
+            prediv: PllPreDiv::DIV1,
+            mul: PllMul::MUL7, // 16 * 7 = 112 MHz
+            divp: None,
+            divq: None,
+            divr: Some(PllRDiv::DIV2), // 112 / 2 = 56 MHz
+        });
+        config.rcc.ls = LsConfig::default_lsi();
+    }
+
+    let p = embassy_stm32::init(config);
+    info!("Hello World!");
+
+    let mut config = Config::default();
+    config.bias = Bias::Third;
+    config.duty = Duty::Quarter;
+    config.target_fps = Hertz(100);
+
+    let mut lcd = Lcd::new(
+        p.LCD,
+        config,
+        p.PC3,
+        [
+            LcdPin::new_com(p.PA8),
+            LcdPin::new_com(p.PA9),
+            LcdPin::new_com(p.PA10),
+            LcdPin::new_seg(p.PB1),
+            LcdPin::new_com(p.PB9),
+            LcdPin::new_seg(p.PB11),
+            LcdPin::new_seg(p.PB14),
+            LcdPin::new_seg(p.PB15),
+            LcdPin::new_seg(p.PC4),
+            LcdPin::new_seg(p.PC5),
+            LcdPin::new_seg(p.PC6),
+            LcdPin::new_seg(p.PC8),
+            LcdPin::new_seg(p.PC9),
+            LcdPin::new_seg(p.PC10),
+            LcdPin::new_seg(p.PC11),
+            LcdPin::new_seg(p.PD8),
+            LcdPin::new_seg(p.PD9),
+            LcdPin::new_seg(p.PD12),
+            LcdPin::new_seg(p.PD13),
+            LcdPin::new_seg(p.PD0),
+            LcdPin::new_seg(p.PD1),
+            LcdPin::new_seg(p.PD3),
+            LcdPin::new_seg(p.PD4),
+            LcdPin::new_seg(p.PD5),
+            LcdPin::new_seg(p.PD6),
+            LcdPin::new_seg(p.PE7),
+            LcdPin::new_seg(p.PE8),
+            LcdPin::new_seg(p.PE9),
+        ],
+    );
+
+    lcd.set_blink(BlinkSelector::All, BlinkFreq::Hz4);
+    {
+        let mut buffer = DisplayBuffer::new();
+        for i in 0..4 {
+            buffer.write_colon(i);
+            buffer.write(&mut lcd);
+            embassy_time::Timer::after_millis(200).await;
+            buffer.write_dot(i);
+            buffer.write(&mut lcd);
+            embassy_time::Timer::after_millis(200).await;
+        }
+        for i in 0..4 {
+            buffer.write_bar(i);
+            buffer.write(&mut lcd);
+            embassy_time::Timer::after_millis(200).await;
+        }
+    }
+
+    embassy_time::Timer::after_millis(1000).await;
+
+    lcd.set_blink(BlinkSelector::None, BlinkFreq::Hz4);
+
+    const MESSAGE: &str = "Hello embassy people. Hope you like this LCD demo :}      ";
+    loop {
+        print_message(MESSAGE, &mut lcd, Duration::from_millis(250)).await;
+        print_message(characters::ALL_CHARS, &mut lcd, Duration::from_millis(500)).await;
+    }
+}
+
+async fn print_message(message: &str, lcd: &mut Lcd<'_, LCD>, delay: Duration) {
+    let mut display_buffer = DisplayBuffer::new();
+
+    let mut char_buffer = [' '; 6];
+    for char in message.chars() {
+        char_buffer.copy_within(1.., 0);
+        char_buffer[5] = char;
+
+        display_buffer.clear();
+        for (i, char) in char_buffer.iter().enumerate() {
+            display_buffer.write_char(i, *char);
+        }
+        display_buffer.write(lcd);
+
+        embassy_time::Timer::after(delay).await;
+    }
+}
+
+/// Display layout for the U0-DK
+mod display_layout {
+    // Character layout. There are 6 characters, left-to-right
+    //         T
+    //     ─────────
+    //    │    N    │
+    //    │ │  │  │ │
+    // TL │ └┐ │ ┌┘ │ TR
+    //    │NW│ │ │NE│
+    //    │    │    │
+    //     W─── ───E
+    //    │    │    │
+    //    │SW│ │ │SE│
+    // BL │ ┌┘ │ └┐ │ BR
+    //    │ │  │  │ │
+    //    │    S    │
+    //     ─────────
+    //         B
+
+    pub const CHAR_N_COM: u8 = 3;
+    pub const CHAR_N_SEG: [u8; 6] = [39, 37, 35, 48, 26, 33];
+    pub const CHAR_NW_COM: u8 = 3;
+    pub const CHAR_NW_SEG: [u8; 6] = [49, 38, 36, 34, 27, 24];
+    pub const CHAR_W_COM: u8 = 0;
+    pub const CHAR_W_SEG: [u8; 6] = CHAR_NW_SEG;
+    pub const CHAR_SW_COM: u8 = 2;
+    pub const CHAR_SW_SEG: [u8; 6] = CHAR_NW_SEG;
+    pub const CHAR_S_COM: u8 = 2;
+    pub const CHAR_S_SEG: [u8; 6] = [22, 6, 46, 11, 15, 29];
+    pub const CHAR_SE_COM: u8 = 3;
+    pub const CHAR_SE_SEG: [u8; 6] = CHAR_S_SEG;
+    pub const CHAR_E_COM: u8 = 0;
+    pub const CHAR_E_SEG: [u8; 6] = [23, 45, 47, 14, 28, 32];
+    pub const CHAR_NE_COM: u8 = 2;
+    pub const CHAR_NE_SEG: [u8; 6] = CHAR_N_SEG;
+    pub const CHAR_T_COM: u8 = 1;
+    pub const CHAR_T_SEG: [u8; 6] = CHAR_N_SEG;
+    pub const CHAR_TL_COM: u8 = 1;
+    pub const CHAR_TL_SEG: [u8; 6] = CHAR_NW_SEG;
+    pub const CHAR_BL_COM: u8 = 0;
+    pub const CHAR_BL_SEG: [u8; 6] = CHAR_S_SEG;
+    pub const CHAR_B_COM: u8 = 1;
+    pub const CHAR_B_SEG: [u8; 6] = CHAR_S_SEG;
+    pub const CHAR_BR_COM: u8 = 1;
+    pub const CHAR_BR_SEG: [u8; 6] = CHAR_E_SEG;
+    pub const CHAR_TR_COM: u8 = 0;
+    pub const CHAR_TR_SEG: [u8; 6] = CHAR_N_SEG;
+
+    pub const COLON_COM: u8 = 2;
+    pub const COLON_SEG: [u8; 4] = [23, 45, 47, 14];
+    pub const DOT_COM: u8 = 3;
+    pub const DOT_SEG: [u8; 4] = COLON_SEG;
+    /// COM + SEG, bar from top to bottom
+    pub const BAR: [(u8, u8); 4] = [(2, 28), (3, 28), (2, 32), (3, 32)];
+}
+
+mod characters {
+    use super::CharSegment::{self, *};
+
+    pub const CHAR_0: &[CharSegment] = &[T, TL, BL, B, BR, TR, NW, SE];
+    pub const CHAR_1: &[CharSegment] = &[NE, TR, BR];
+    pub const CHAR_2: &[CharSegment] = &[T, BL, B, TR, E, W];
+    pub const CHAR_3: &[CharSegment] = &[T, B, BR, TR, E];
+    pub const CHAR_4: &[CharSegment] = &[TL, BR, TR, E, W];
+    pub const CHAR_5: &[CharSegment] = &[T, TL, B, BR, E, W];
+    pub const CHAR_6: &[CharSegment] = &[T, TL, BL, B, BR, E, W];
+    pub const CHAR_7: &[CharSegment] = &[T, NE, S];
+    pub const CHAR_8: &[CharSegment] = &[T, TL, BL, B, BR, TR, E, W];
+    pub const CHAR_9: &[CharSegment] = &[T, TL, BR, TR, E, W];
+
+    pub const CHAR_COLON: &[CharSegment] = &[N, S];
+    pub const CHAR_SEMICOLON: &[CharSegment] = &[N, SW];
+    pub const CHAR_EQUALS: &[CharSegment] = &[E, W, B];
+    pub const CHAR_SLASH: &[CharSegment] = &[SW, NE];
+    pub const CHAR_BACKSLASH: &[CharSegment] = &[SE, NW];
+    pub const CHAR_PLUS: &[CharSegment] = &[N, E, S, W];
+    pub const CHAR_STAR: &[CharSegment] = &[NE, N, NW, SE, S, SW];
+    pub const CHAR_QUOTE: &[CharSegment] = &[N];
+    pub const CHAR_BACKTICK: &[CharSegment] = &[NW];
+    pub const CHAR_DASH: &[CharSegment] = &[W, E];
+    pub const CHAR_COMMA: &[CharSegment] = &[SW];
+    pub const CHAR_DOT: &[CharSegment] = &[S];
+    pub const CHAR_CURLYOPEN: &[CharSegment] = &[T, NW, W, SW, B];
+    pub const CHAR_CURLYCLOSE: &[CharSegment] = &[T, NE, E, SE, B];
+    pub const CHAR_AMPERSAND: &[CharSegment] = &[T, NE, NW, W, BL, B, SE];
+
+    pub const CHAR_A: &[CharSegment] = &[T, TL, TR, E, W, BL, BR];
+    pub const CHAR_B: &[CharSegment] = &[T, TR, BR, B, N, S, E];
+    pub const CHAR_C: &[CharSegment] = &[T, TL, BL, B];
+    pub const CHAR_D: &[CharSegment] = &[T, TR, BR, B, N, S];
+    pub const CHAR_E: &[CharSegment] = &[T, TL, BL, B, W];
+    pub const CHAR_F: &[CharSegment] = &[T, TL, BL, W];
+    pub const CHAR_G: &[CharSegment] = &[T, TL, BL, B, BR, E];
+    pub const CHAR_H: &[CharSegment] = &[TL, BL, E, W, TR, BR];
+    pub const CHAR_I: &[CharSegment] = &[T, N, S, B];
+    pub const CHAR_J: &[CharSegment] = &[TR, BR, B, BL];
+    pub const CHAR_K: &[CharSegment] = &[TL, BL, W, NE, SE];
+    pub const CHAR_L: &[CharSegment] = &[TL, BL, B];
+    pub const CHAR_M: &[CharSegment] = &[BL, TL, NW, NE, TR, BR];
+    pub const CHAR_N: &[CharSegment] = &[BL, TL, NW, SE, BR, TR];
+    pub const CHAR_O: &[CharSegment] = &[T, TL, BL, B, BR, TR];
+    pub const CHAR_P: &[CharSegment] = &[BL, TL, T, TR, E, W];
+    pub const CHAR_Q: &[CharSegment] = &[T, TL, BL, B, BR, TR, SE];
+    pub const CHAR_R: &[CharSegment] = &[BL, TL, T, TR, E, W, SE];
+    pub const CHAR_S: &[CharSegment] = &[T, NW, E, BR, B];
+    pub const CHAR_T: &[CharSegment] = &[T, N, S];
+    pub const CHAR_U: &[CharSegment] = &[TL, BL, B, BR, TR];
+    pub const CHAR_V: &[CharSegment] = &[TL, BL, SW, NE];
+    pub const CHAR_W: &[CharSegment] = &[TL, BL, SW, SE, BR, TR];
+    pub const CHAR_X: &[CharSegment] = &[NE, NW, SE, SW];
+    pub const CHAR_Y: &[CharSegment] = &[NE, NW, S];
+    pub const CHAR_Z: &[CharSegment] = &[T, NE, SW, B];
+
+    pub const CHAR_UNKNOWN: &[CharSegment] = &[N, NW, W, SW, S, SE, E, NE, T, TL, BL, B, BR, TR];
+
+    pub const ALL_CHARS: &str =
+        "0 1 2 3 4 5 6 7 8 9 : ; = / \\ + * ' ` - , . { } & A B C D E F G H I J K L M N O P Q R S T U V W X Y Z � ";
+
+    pub fn get_char_segments(val: char) -> &'static [CharSegment] {
+        match val {
+            val if val.is_whitespace() => &[],
+
+            '0' => CHAR_0,
+            '1' => CHAR_1,
+            '2' => CHAR_2,
+            '3' => CHAR_3,
+            '4' => CHAR_4,
+            '5' => CHAR_5,
+            '6' => CHAR_6,
+            '7' => CHAR_7,
+            '8' => CHAR_8,
+            '9' => CHAR_9,
+
+            ':' => CHAR_COLON,
+            ';' => CHAR_SEMICOLON,
+            '=' => CHAR_EQUALS,
+            '/' => CHAR_SLASH,
+            '\\' => CHAR_BACKSLASH,
+            '+' => CHAR_PLUS,
+            '*' => CHAR_STAR,
+            '\'' => CHAR_QUOTE,
+            '`' => CHAR_BACKTICK,
+            '-' => CHAR_DASH,
+            ',' => CHAR_COMMA,
+            '.' => CHAR_DOT,
+            '{' => CHAR_CURLYOPEN,
+            '}' => CHAR_CURLYCLOSE,
+            '&' => CHAR_AMPERSAND,
+
+            'A' | 'a' => CHAR_A,
+            'B' | 'b' => CHAR_B,
+            'C' | 'c' => CHAR_C,
+            'D' | 'd' => CHAR_D,
+            'E' | 'e' => CHAR_E,
+            'F' | 'f' => CHAR_F,
+            'G' | 'g' => CHAR_G,
+            'H' | 'h' => CHAR_H,
+            'I' | 'i' => CHAR_I,
+            'J' | 'j' => CHAR_J,
+            'K' | 'k' => CHAR_K,
+            'L' | 'l' => CHAR_L,
+            'M' | 'm' => CHAR_M,
+            'N' | 'n' => CHAR_N,
+            'O' | 'o' => CHAR_O,
+            'P' | 'p' => CHAR_P,
+            'Q' | 'q' => CHAR_Q,
+            'R' | 'r' => CHAR_R,
+            'S' | 's' => CHAR_S,
+            'T' | 't' => CHAR_T,
+            'U' | 'u' => CHAR_U,
+            'V' | 'v' => CHAR_V,
+            'W' | 'w' => CHAR_W,
+            'X' | 'x' => CHAR_X,
+            'Y' | 'y' => CHAR_Y,
+            'Z' | 'z' => CHAR_Z,
+
+            _ => CHAR_UNKNOWN,
+        }
+    }
+}
+
+pub struct DisplayBuffer {
+    pixels: [u64; 4],
+}
+
+impl DisplayBuffer {
+    pub const fn new() -> Self {
+        Self { pixels: [0; 4] }
+    }
+
+    pub fn clear(&mut self) {
+        *self = Self::new();
+    }
+
+    fn write_char_segment(&mut self, index: usize, value: CharSegment) {
+        defmt::assert!(index < 6);
+        let (com, segments) = value.get_com_seg();
+        self.pixels[com as usize] |= 1 << segments[index];
+    }
+
+    pub fn write_char(&mut self, index: usize, val: char) {
+        let segments = characters::get_char_segments(val);
+
+        for segment in segments {
+            self.write_char_segment(index, *segment);
+        }
+    }
+
+    pub fn write(&self, lcd: &mut Lcd<'_, LCD>) {
+        lcd.write_com_segments(0, self.pixels[0]);
+        lcd.write_com_segments(1, self.pixels[1]);
+        lcd.write_com_segments(2, self.pixels[2]);
+        lcd.write_com_segments(3, self.pixels[3]);
+        lcd.submit_frame();
+    }
+
+    pub fn write_colon(&mut self, index: usize) {
+        defmt::assert!(index < 4);
+        self.pixels[display_layout::COLON_COM as usize] |= 1 << display_layout::COLON_SEG[index];
+    }
+
+    pub fn write_dot(&mut self, index: usize) {
+        defmt::assert!(index < 4);
+        self.pixels[display_layout::DOT_COM as usize] |= 1 << display_layout::DOT_SEG[index];
+    }
+
+    pub fn write_bar(&mut self, index: usize) {
+        defmt::assert!(index < 4);
+        let (bar_com, bar_seg) = display_layout::BAR[index];
+        self.pixels[bar_com as usize] |= 1 << bar_seg;
+    }
+}
+
+impl Default for DisplayBuffer {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+#[derive(Debug, Clone, Copy)]
+enum CharSegment {
+    /// North
+    N,
+    /// North west
+    NW,
+    /// West
+    W,
+    /// South west
+    SW,
+    /// South
+    S,
+    /// South East
+    SE,
+    /// East
+    E,
+    /// North East
+    NE,
+    /// Top
+    T,
+    /// Top left
+    TL,
+    /// Bottom left
+    BL,
+    /// Bottom
+    B,
+    /// Bottom right
+    BR,
+    /// Top right
+    TR,
+}
+
+impl CharSegment {
+    fn get_com_seg(&self) -> (u8, [u8; 6]) {
+        match self {
+            CharSegment::N => (display_layout::CHAR_N_COM, display_layout::CHAR_N_SEG),
+            CharSegment::NW => (display_layout::CHAR_NW_COM, display_layout::CHAR_NW_SEG),
+            CharSegment::W => (display_layout::CHAR_W_COM, display_layout::CHAR_W_SEG),
+            CharSegment::SW => (display_layout::CHAR_SW_COM, display_layout::CHAR_SW_SEG),
+            CharSegment::S => (display_layout::CHAR_S_COM, display_layout::CHAR_S_SEG),
+            CharSegment::SE => (display_layout::CHAR_SE_COM, display_layout::CHAR_SE_SEG),
+            CharSegment::E => (display_layout::CHAR_E_COM, display_layout::CHAR_E_SEG),
+            CharSegment::NE => (display_layout::CHAR_NE_COM, display_layout::CHAR_NE_SEG),
+            CharSegment::T => (display_layout::CHAR_T_COM, display_layout::CHAR_T_SEG),
+            CharSegment::TL => (display_layout::CHAR_TL_COM, display_layout::CHAR_TL_SEG),
+            CharSegment::BL => (display_layout::CHAR_BL_COM, display_layout::CHAR_BL_SEG),
+            CharSegment::B => (display_layout::CHAR_B_COM, display_layout::CHAR_B_SEG),
+            CharSegment::BR => (display_layout::CHAR_BR_COM, display_layout::CHAR_BR_SEG),
+            CharSegment::TR => (display_layout::CHAR_TR_COM, display_layout::CHAR_TR_SEG),
+        }
+    }
+}
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index 8fcb6b2b4..496a9de18 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -32,7 +32,7 @@ stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma", "rng", "hash", "dual-ba
 stm32u585ai = ["embassy-stm32/stm32u585ai", "spi-v345", "chrono", "rng", "hash", "cordic"]
 stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "spi-v345", "chrono", "rng", "hash"] # FIXME: cordic test cause it crash
 stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng", "hsem", "stop"]
-stm32wba52cg = ["embassy-stm32/stm32wba52cg", "spi-v345", "chrono", "rng", "hash"]
+stm32wba52cg = ["embassy-stm32/stm32wba52cg", "spi-v345", "chrono", "rng", "hash", "adc"]
 stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono", "hsem"]
 stm32f091rc = ["embassy-stm32/stm32f091rc", "cm0", "not-gpdma", "chrono"]
 stm32h503rb = ["embassy-stm32/stm32h503rb", "spi-v345", "rng", "stop"]
@@ -56,6 +56,7 @@ mac = ["dep:embassy-stm32-wpan", "embassy-stm32-wpan/mac"]
 embassy-stm32-wpan = []
 not-gpdma = []
 dac = []
+adc = []
 ucpd = []
 cordic = ["dep:num-traits"]
 hsem = []
@@ -111,6 +112,11 @@ path = "src/bin/afio.rs"
 required-features = [ "afio",]
 
 [[bin]]
+name = "adc"
+path = "src/bin/adc.rs"
+required-features = [ "adc",]
+
+[[bin]]
 name = "can"
 path = "src/bin/can.rs"
 required-features = [ "can",]
diff --git a/tests/stm32/src/bin/adc.rs b/tests/stm32/src/bin/adc.rs
new file mode 100644
index 000000000..6cedc6498
--- /dev/null
+++ b/tests/stm32/src/bin/adc.rs
@@ -0,0 +1,39 @@
+#![no_std]
+#![no_main]
+
+// required-features: dac
+
+#[path = "../common.rs"]
+mod common;
+
+use common::*;
+use embassy_executor::Spawner;
+use embassy_stm32::adc::{Adc, SampleTime};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Initialize the board and obtain a Peripherals instance
+    let p: embassy_stm32::Peripherals = init();
+
+    let adc = peri!(p, ADC);
+    let mut adc_pin = peri!(p, DAC_PIN);
+
+    let mut adc = Adc::new_adc4(adc);
+
+    // Now wait a little to obtain a stable value
+    Timer::after_millis(30).await;
+    let _ = adc.blocking_read(&mut adc_pin, SampleTime::from_bits(0));
+
+    for _ in 0..=255 {
+        // Now wait a little to obtain a stable value
+        Timer::after_millis(30).await;
+
+        // Need to steal the peripherals here because PA4 is obviously in use already
+        let _ = adc.blocking_read(&mut adc_pin, SampleTime::from_bits(0));
+    }
+
+    info!("Test OK");
+    cortex_m::asm::bkpt();
+}
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 096cce947..9f88b182a 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -259,6 +259,7 @@ define_peris!(
 define_peris!(
     UART = LPUART1, UART_TX = PB5, UART_RX = PA10, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
     SPI = SPI1, SPI_SCK = PB4, SPI_MOSI = PA15, SPI_MISO = PB3, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
+    ADC = ADC4, DAC_PIN = PA0,
     @irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
 );
 #[cfg(feature = "stm32h7s3l8")]