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authorAlexandros Liarokapis <[email protected]>2024-05-28 12:50:24 +0300
committerAlexandros Liarokapis <[email protected]>2024-05-28 12:50:24 +0300
commit46fc15783d226d66aa93e38c0b36c8cac9b71700 (patch)
tree3641c146646b55b5e8f4dccb5144bfdd4ec0b5ab
parent9a6ed79ad124c8a22f6833c2c4f9637661a5bbdb (diff)
add spi_v4 and spi_v5 support but block i2scfg rx-only configuration
-rw-r--r--embassy-stm32/src/spi/mod.rs12
1 files changed, 7 insertions, 5 deletions
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index d9b6f0003..109b2738b 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -508,7 +508,7 @@ impl<'d> Spi<'d, Async> {
508 peri: impl Peripheral<P = T> + 'd, 508 peri: impl Peripheral<P = T> + 'd,
509 sck: impl Peripheral<P = impl SckPin<T>> + 'd, 509 sck: impl Peripheral<P = impl SckPin<T>> + 'd,
510 miso: impl Peripheral<P = impl MisoPin<T>> + 'd, 510 miso: impl Peripheral<P = impl MisoPin<T>> + 'd,
511 #[cfg(any(spi_v1, spi_f1, spi_v4, spi_v5))] tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd, 511 #[cfg(any(spi_v1, spi_f1, spi_v2))] tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
512 rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd, 512 rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
513 config: Config, 513 config: Config,
514 ) -> Self { 514 ) -> Self {
@@ -517,9 +517,9 @@ impl<'d> Spi<'d, Async> {
517 new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()), 517 new_pin!(sck, AFType::OutputPushPull, Speed::VeryHigh, config.sck_pull_mode()),
518 None, 518 None,
519 new_pin!(miso, AFType::Input, Speed::VeryHigh), 519 new_pin!(miso, AFType::Input, Speed::VeryHigh),
520 #[cfg(any(spi_v1, spi_f1, spi_v4, spi_v5))] 520 #[cfg(any(spi_v1, spi_f1, spi_v2))]
521 new_dma!(tx_dma), 521 new_dma!(tx_dma),
522 #[cfg(any(spi_v2, spi_v3))] 522 #[cfg(any(spi_v3, spi_v4, spi_v5))]
523 None, 523 None,
524 new_dma!(rx_dma), 524 new_dma!(rx_dma),
525 config, 525 config,
@@ -626,7 +626,7 @@ impl<'d> Spi<'d, Async> {
626 } 626 }
627 627
628 /// SPI read, using DMA. 628 /// SPI read, using DMA.
629 #[cfg(any(spi_v2, spi_v3))] 629 #[cfg(any(spi_v3, spi_v4, spi_v5))]
630 pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> { 630 pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
631 if data.is_empty() { 631 if data.is_empty() {
632 return Ok(()); 632 return Ok(());
@@ -644,6 +644,7 @@ impl<'d> Spi<'d, Async> {
644 prev 644 prev
645 }); 645 });
646 646
647 #[cfg(spi_v3)]
647 let i2scfg = regs.i2scfgr().modify(|w| { 648 let i2scfg = regs.i2scfgr().modify(|w| {
648 w.i2smod().then(|| { 649 w.i2smod().then(|| {
649 let prev = w.i2scfg(); 650 let prev = w.i2scfg();
@@ -713,6 +714,7 @@ impl<'d> Spi<'d, Async> {
713 w.set_tsize(tsize); 714 w.set_tsize(tsize);
714 }); 715 });
715 716
717 #[cfg(spi_v3)]
716 if let Some(i2scfg) = i2scfg { 718 if let Some(i2scfg) = i2scfg {
717 regs.i2scfgr().modify(|w| { 719 regs.i2scfgr().modify(|w| {
718 w.set_i2scfg(i2scfg); 720 w.set_i2scfg(i2scfg);
@@ -723,7 +725,7 @@ impl<'d> Spi<'d, Async> {
723 } 725 }
724 726
725 /// SPI read, using DMA. 727 /// SPI read, using DMA.
726 #[cfg(any(spi_v1, spi_f1, spi_v4, spi_v5))] 728 #[cfg(any(spi_v1, spi_f1, spi_v2))]
727 pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> { 729 pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
728 if data.is_empty() { 730 if data.is_empty() {
729 return Ok(()); 731 return Ok(());