stm32/rcc: unify naming sysclk field to `sys`, enum to `Sysclk`.

20 files changed, 74 insertions, 74 deletions

diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index ca1222185..ec6ec34e8 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -9,7 +9,7 @@ pub const HSI_FREQ: Hertz = Hertz(48_000_000);
 
 /// System clock mux source
 #[derive(Clone, Copy)]
-pub enum ClockSrc {
+pub enum Sysclk {
     HSE(Hertz),
     HSI(HSIPrescaler),
     LSI,
@@ -17,7 +17,7 @@ pub enum ClockSrc {
 
 /// Clocks configutation
 pub struct Config {
-    pub mux: ClockSrc,
+    pub sys: Sysclk,
     pub ahb_pre: AHBPrescaler,
     pub apb_pre: APBPrescaler,
     pub ls: super::LsConfig,
@@ -27,7 +27,7 @@ impl Default for Config {
     #[inline]
     fn default() -> Config {
         Config {
-            mux: ClockSrc::HSI(HSIPrescaler::DIV1),
+            sys: Sysclk::HSI(HSIPrescaler::DIV1),
             ahb_pre: AHBPrescaler::DIV1,
             apb_pre: APBPrescaler::DIV1,
             ls: Default::default(),
@@ -36,8 +36,8 @@ impl Default for Config {
 }
 
 pub(crate) unsafe fn init(config: Config) {
-    let (sys_clk, sw) = match config.mux {
-        ClockSrc::HSI(div) => {
+    let (sys_clk, sw) = match config.sys {
+        Sysclk::HSI(div) => {
             // Enable HSI
             RCC.cr().write(|w| {
                 w.set_hsidiv(div);
@@ -47,14 +47,14 @@ pub(crate) unsafe fn init(config: Config) {
 
             (HSI_FREQ / div, Sw::HSI)
         }
-        ClockSrc::HSE(freq) => {
+        Sysclk::HSE(freq) => {
             // Enable HSE
             RCC.cr().write(|w| w.set_hseon(true));
             while !RCC.cr().read().hserdy() {}
 
             (freq, Sw::HSE)
         }
-        ClockSrc::LSI => {
+        Sysclk::LSI => {
             // Enable LSI
             RCC.csr2().write(|w| w.set_lsion(true));
             while !RCC.csr2().read().lsirdy() {}
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index e3cd46fb9..0b1f34a20 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -19,7 +19,7 @@ pub enum HseMode {
 
 /// System clock mux source
 #[derive(Clone, Copy)]
-pub enum ClockSrc {
+pub enum Sysclk {
     HSE(Hertz, HseMode),
     HSI(HSIPrescaler),
     PLL(PllConfig),
@@ -89,7 +89,7 @@ pub enum UsbSrc {
 
 /// Clocks configutation
 pub struct Config {
-    pub mux: ClockSrc,
+    pub sys: Sysclk,
     pub ahb_pre: AHBPrescaler,
     pub apb_pre: APBPrescaler,
     pub low_power_run: bool,
@@ -102,7 +102,7 @@ impl Default for Config {
     #[inline]
     fn default() -> Config {
         Config {
-            mux: ClockSrc::HSI(HSIPrescaler::DIV1),
+            sys: Sysclk::HSI(HSIPrescaler::DIV1),
             ahb_pre: AHBPrescaler::DIV1,
             apb_pre: APBPrescaler::DIV1,
             low_power_run: false,
@@ -202,8 +202,8 @@ pub(crate) unsafe fn init(config: Config) {
     let mut pll1_q_freq = None;
     let mut pll1_p_freq = None;
 
-    let (sys_clk, sw) = match config.mux {
-        ClockSrc::HSI(div) => {
+    let (sys_clk, sw) = match config.sys {
+        Sysclk::HSI(div) => {
             // Enable HSI
             RCC.cr().write(|w| {
                 w.set_hsidiv(div);
@@ -213,7 +213,7 @@ pub(crate) unsafe fn init(config: Config) {
 
             (HSI_FREQ / div, Sw::HSI)
         }
-        ClockSrc::HSE(freq, mode) => {
+        Sysclk::HSE(freq, mode) => {
             // Enable HSE
             RCC.cr().write(|w| {
                 w.set_hseon(true);
@@ -223,7 +223,7 @@ pub(crate) unsafe fn init(config: Config) {
 
             (freq, Sw::HSE)
         }
-        ClockSrc::PLL(pll) => {
+        Sysclk::PLL(pll) => {
             let (r_freq, q_freq, p_freq) = pll.init();
 
             pll1_q_freq = q_freq;
@@ -231,7 +231,7 @@ pub(crate) unsafe fn init(config: Config) {
 
             (r_freq, Sw::PLL1_R)
         }
-        ClockSrc::LSI => {
+        Sysclk::LSI => {
             // Enable LSI
             RCC.csr().write(|w| w.set_lsion(true));
             while !RCC.csr().read().lsirdy() {}
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index 04ea81ec4..aa4245d4e 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -7,7 +7,7 @@ pub use crate::pac::rcc::vals::Adcsel as AdcClockSource;
 pub use crate::pac::rcc::vals::Clk48sel as Clk48Src;
 #[cfg(any(stm32wb, stm32wl))]
 pub use crate::pac::rcc::vals::Hsepre as HsePrescaler;
-pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange as MSIRange, Ppre as APBPrescaler, Sw as ClockSrc};
+pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange as MSIRange, Ppre as APBPrescaler, Sw as Sysclk};
 use crate::pac::{FLASH, RCC};
 use crate::time::Hertz;
 
@@ -50,7 +50,7 @@ pub struct Config {
     pub pllsai2: Option<Pll>,
 
     // sysclk, buses.
-    pub mux: ClockSrc,
+    pub sys: Sysclk,
     pub ahb_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
@@ -80,7 +80,7 @@ impl Default for Config {
             hse: None,
             hsi: false,
             msi: Some(MSIRange::RANGE4M),
-            mux: ClockSrc::MSI,
+            sys: Sysclk::MSI,
             ahb_pre: AHBPrescaler::DIV1,
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
@@ -113,7 +113,7 @@ pub const WPAN_DEFAULT: Config = Config {
         mode: HseMode::Oscillator,
         prescaler: HsePrescaler::DIV1,
     }),
-    mux: ClockSrc::PLL1_R,
+    sys: Sysclk::PLL1_R,
     #[cfg(crs)]
     hsi48: Some(super::Hsi48Config { sync_from_usb: false }),
     msi: None,
@@ -161,11 +161,11 @@ pub(crate) unsafe fn init(config: Config) {
         // Turn on MSI and configure it to 4MHz.
         msi_enable(MSIRange::RANGE4M)
     }
-    if RCC.cfgr().read().sws() != ClockSrc::MSI {
+    if RCC.cfgr().read().sws() != Sysclk::MSI {
         // Set MSI as a clock source, reset prescalers.
         RCC.cfgr().write_value(Cfgr::default());
         // Wait for clock switch status bits to change.
-        while RCC.cfgr().read().sws() != ClockSrc::MSI {}
+        while RCC.cfgr().read().sws() != Sysclk::MSI {}
     }
 
     // Set voltage scale
@@ -260,11 +260,11 @@ pub(crate) unsafe fn init(config: Config) {
     #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
     let pllsai2 = init_pll(PllInstance::Pllsai2, config.pllsai2, &pll_input);
 
-    let sys_clk = match config.mux {
-        ClockSrc::HSE => hse.unwrap(),
-        ClockSrc::HSI => hsi.unwrap(),
-        ClockSrc::MSI => msi.unwrap(),
-        ClockSrc::PLL1_R => pll.r.unwrap(),
+    let sys_clk = match config.sys {
+        Sysclk::HSE => hse.unwrap(),
+        Sysclk::HSI => hsi.unwrap(),
+        Sysclk::MSI => msi.unwrap(),
+        Sysclk::PLL1_R => pll.r.unwrap(),
     };
 
     #[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
@@ -350,12 +350,12 @@ pub(crate) unsafe fn init(config: Config) {
     while FLASH.acr().read().latency() != latency {}
 
     RCC.cfgr().modify(|w| {
-        w.set_sw(config.mux);
+        w.set_sw(config.sys);
         w.set_hpre(config.ahb_pre);
         w.set_ppre1(config.apb1_pre);
         w.set_ppre2(config.apb2_pre);
     });
-    while RCC.cfgr().read().sws() != config.mux {}
+    while RCC.cfgr().read().sws() != config.sys {}
 
     #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
     RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source));
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 72613f0f3..43138f05c 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -1,7 +1,7 @@
 pub use crate::pac::pwr::vals::Vos as VoltageScale;
 pub use crate::pac::rcc::vals::{
     Hpre as AHBPrescaler, Msirange, Msirange as MSIRange, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul,
-    Pllsrc as PllSource, Ppre as APBPrescaler, Sw as ClockSrc,
+    Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
 };
 use crate::pac::rcc::vals::{Hseext, Msirgsel, Pllmboost, Pllrge};
 use crate::pac::{FLASH, PWR, RCC};
@@ -72,7 +72,7 @@ pub struct Config {
     pub pll3: Option<Pll>,
 
     // sysclk, buses.
-    pub mux: ClockSrc,
+    pub sys: Sysclk,
     pub ahb_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
@@ -97,7 +97,7 @@ impl Default for Config {
             pll1: None,
             pll2: None,
             pll3: None,
-            mux: ClockSrc::MSIS,
+            sys: Sysclk::MSIS,
             ahb_pre: AHBPrescaler::DIV1,
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
@@ -181,11 +181,11 @@ pub(crate) unsafe fn init(config: Config) {
     let pll2 = init_pll(PllInstance::Pll2, config.pll2, &pll_input, config.voltage_range);
     let pll3 = init_pll(PllInstance::Pll3, config.pll3, &pll_input, config.voltage_range);
 
-    let sys_clk = match config.mux {
-        ClockSrc::HSE => hse.unwrap(),
-        ClockSrc::HSI => hsi.unwrap(),
-        ClockSrc::MSIS => msi.unwrap(),
-        ClockSrc::PLL1_R => pll1.r.unwrap(),
+    let sys_clk = match config.sys {
+        Sysclk::HSE => hse.unwrap(),
+        Sysclk::HSI => hsi.unwrap(),
+        Sysclk::MSIS => msi.unwrap(),
+        Sysclk::PLL1_R => pll1.r.unwrap(),
     };
 
     // Do we need the EPOD booster to reach the target clock speed per § 10.5.4?
@@ -230,8 +230,8 @@ pub(crate) unsafe fn init(config: Config) {
     });
 
     // Switch the system clock source
-    RCC.cfgr1().modify(|w| w.set_sw(config.mux));
-    while RCC.cfgr1().read().sws() != config.mux {}
+    RCC.cfgr1().modify(|w| w.set_sw(config.sys));
+    while RCC.cfgr1().read().sws() != config.sys {}
 
     // Configure the bus prescalers
     RCC.cfgr2().modify(|w| {
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index fbf2d1cf9..9d5dcfc4b 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -1,7 +1,7 @@
 pub use crate::pac::pwr::vals::Vos as VoltageScale;
 use crate::pac::rcc::regs::Cfgr1;
 pub use crate::pac::rcc::vals::{
-    Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as ClockSrc,
+    Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as Sysclk,
 };
 use crate::pac::{FLASH, RCC};
 use crate::time::Hertz;
@@ -23,7 +23,7 @@ pub struct Config {
     pub hse: Option<Hse>,
 
     // sysclk, buses.
-    pub mux: ClockSrc,
+    pub sys: Sysclk,
     pub ahb_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
@@ -43,7 +43,7 @@ impl Default for Config {
         Config {
             hse: None,
             hsi: true,
-            mux: ClockSrc::HSI,
+            sys: Sysclk::HSI,
             ahb_pre: AHBPrescaler::DIV1,
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
@@ -65,11 +65,11 @@ pub(crate) unsafe fn init(config: Config) {
     if !RCC.cr().read().hsion() {
         hsi_enable()
     }
-    if RCC.cfgr1().read().sws() != ClockSrc::HSI {
+    if RCC.cfgr1().read().sws() != Sysclk::HSI {
         // Set HSI as a clock source, reset prescalers.
         RCC.cfgr1().write_value(Cfgr1::default());
         // Wait for clock switch status bits to change.
-        while RCC.cfgr1().read().sws() != ClockSrc::HSI {}
+        while RCC.cfgr1().read().sws() != Sysclk::HSI {}
     }
 
     // Set voltage scale
@@ -94,11 +94,11 @@ pub(crate) unsafe fn init(config: Config) {
         HSE_FREQ
     });
 
-    let sys_clk = match config.mux {
-        ClockSrc::HSE => hse.unwrap(),
-        ClockSrc::HSI => hsi.unwrap(),
-        ClockSrc::_RESERVED_1 => unreachable!(),
-        ClockSrc::PLL1_R => todo!(),
+    let sys_clk = match config.sys {
+        Sysclk::HSE => hse.unwrap(),
+        Sysclk::HSI => hsi.unwrap(),
+        Sysclk::_RESERVED_1 => unreachable!(),
+        Sysclk::PLL1_R => todo!(),
     };
 
     assert!(sys_clk.0 <= 100_000_000);
@@ -142,9 +142,9 @@ pub(crate) unsafe fn init(config: Config) {
     // TODO: Set the SRAM wait states
 
     RCC.cfgr1().modify(|w| {
-        w.set_sw(config.mux);
+        w.set_sw(config.sys);
     });
-    while RCC.cfgr1().read().sws() != config.mux {}
+    while RCC.cfgr1().read().sws() != config.sys {}
 
     RCC.cfgr2().modify(|w| {
         w.set_hpre(config.ahb_pre);
diff --git a/examples/stm32g0/src/bin/hf_timer.rs b/examples/stm32g0/src/bin/hf_timer.rs
index 78a779e29..3f63d0dfd 100644
--- a/examples/stm32g0/src/bin/hf_timer.rs
+++ b/examples/stm32g0/src/bin/hf_timer.rs
@@ -5,7 +5,7 @@ use defmt::info;
 use embassy_executor::Spawner;
 use embassy_stm32::gpio::OutputType;
 use embassy_stm32::pac::rcc::vals::Tim1sel;
-use embassy_stm32::rcc::{ClockSrc, Config as RccConfig, PllConfig, PllSource, Pllm, Plln, Pllq, Pllr};
+use embassy_stm32::rcc::{Config as RccConfig, PllConfig, PllSource, Pllm, Plln, Pllq, Pllr, Sysclk};
 use embassy_stm32::time::khz;
 use embassy_stm32::timer::complementary_pwm::{ComplementaryPwm, ComplementaryPwmPin};
 use embassy_stm32::timer::simple_pwm::PwmPin;
@@ -16,7 +16,7 @@ use {defmt_rtt as _, panic_probe as _};
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut rcc_config = RccConfig::default();
-    rcc_config.mux = ClockSrc::PLL(PllConfig {
+    rcc_config.sys = Sysclk::PLL(PllConfig {
         source: PllSource::HSI,
         m: Pllm::DIV1,
         n: Plln::MUL16,
diff --git a/examples/stm32l1/src/bin/usb_serial.rs b/examples/stm32l1/src/bin/usb_serial.rs
index 7b1e84cbc..f738ea358 100644
--- a/examples/stm32l1/src/bin/usb_serial.rs
+++ b/examples/stm32l1/src/bin/usb_serial.rs
@@ -27,7 +27,7 @@ async fn main(_spawner: Spawner) {
             mul: PllMul::MUL6, // PLLVCO = 16*6 = 96Mhz
             div: PllDiv::DIV3, // 32Mhz clock (16 * 6 / 3)
         });
-        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.sys = Sysclk::PLL1_R;
     }
 
     let p = embassy_stm32::init(config);
diff --git a/examples/stm32l4/src/bin/rng.rs b/examples/stm32l4/src/bin/rng.rs
index 638b3e9e4..14d0e3c1e 100644
--- a/examples/stm32l4/src/bin/rng.rs
+++ b/examples/stm32l4/src/bin/rng.rs
@@ -3,7 +3,7 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::rcc::{ClockSrc, Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv, PllSource};
+use embassy_stm32::rcc::{Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv, PllSource, Sysclk};
 use embassy_stm32::rng::Rng;
 use embassy_stm32::{bind_interrupts, peripherals, rng, Config};
 use {defmt_rtt as _, panic_probe as _};
@@ -15,7 +15,7 @@ bind_interrupts!(struct Irqs {
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
-    config.rcc.mux = ClockSrc::PLL1_R;
+    config.rcc.sys = Sysclk::PLL1_R;
     config.rcc.hsi = true;
     config.rcc.pll = Some(Pll {
         source: PllSource::HSI,
diff --git a/examples/stm32l4/src/bin/rtc.rs b/examples/stm32l4/src/bin/rtc.rs
index 526620bfb..a8a375ab4 100644
--- a/examples/stm32l4/src/bin/rtc.rs
+++ b/examples/stm32l4/src/bin/rtc.rs
@@ -15,7 +15,7 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.sys = Sysclk::PLL1_R;
         config.rcc.hse = Some(Hse {
             freq: Hertz::mhz(8),
             mode: HseMode::Oscillator,
diff --git a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
index 026a3a477..32bfab6eb 100644
--- a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
+++ b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
@@ -75,7 +75,7 @@ async fn main(spawner: Spawner) {
         use embassy_stm32::rcc::*;
         // 80Mhz clock (Source: 8 / SrcDiv: 1 * PllMul 20 / ClkDiv 2)
         // 80MHz highest frequency for flash 0 wait.
-        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.sys = Sysclk::PLL1_R;
         config.rcc.hse = Some(Hse {
             freq: Hertz::mhz(8),
             mode: HseMode::Oscillator,
diff --git a/examples/stm32l4/src/bin/usb_serial.rs b/examples/stm32l4/src/bin/usb_serial.rs
index 8cc9a7aed..9247e56a1 100644
--- a/examples/stm32l4/src/bin/usb_serial.rs
+++ b/examples/stm32l4/src/bin/usb_serial.rs
@@ -23,7 +23,7 @@ async fn main(_spawner: Spawner) {
 
     let mut config = Config::default();
     config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB
-    config.rcc.mux = ClockSrc::PLL1_R;
+    config.rcc.sys = Sysclk::PLL1_R;
     config.rcc.hsi = true;
     config.rcc.pll = Some(Pll {
         source: PllSource::HSI,
diff --git a/examples/stm32l5/src/bin/rng.rs b/examples/stm32l5/src/bin/rng.rs
index 50da6c946..0a644e73d 100644
--- a/examples/stm32l5/src/bin/rng.rs
+++ b/examples/stm32l5/src/bin/rng.rs
@@ -3,7 +3,7 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::rcc::{ClockSrc, Pll, PllMul, PllPreDiv, PllRDiv, PllSource};
+use embassy_stm32::rcc::{Pll, PllMul, PllPreDiv, PllRDiv, PllSource, Sysclk};
 use embassy_stm32::rng::Rng;
 use embassy_stm32::{bind_interrupts, peripherals, rng, Config};
 use {defmt_rtt as _, panic_probe as _};
@@ -16,7 +16,7 @@ bind_interrupts!(struct Irqs {
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     config.rcc.hsi = true;
-    config.rcc.mux = ClockSrc::PLL1_R;
+    config.rcc.sys = Sysclk::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 64Mhz clock (16 / 1 * 8 / 2)
         source: PllSource::HSI,
diff --git a/examples/stm32l5/src/bin/usb_ethernet.rs b/examples/stm32l5/src/bin/usb_ethernet.rs
index 88060b6b0..f6d8b16d0 100644
--- a/examples/stm32l5/src/bin/usb_ethernet.rs
+++ b/examples/stm32l5/src/bin/usb_ethernet.rs
@@ -45,7 +45,7 @@ async fn net_task(stack: &'static Stack<Device<'static, MTU>>) -> ! {
 async fn main(spawner: Spawner) {
     let mut config = Config::default();
     config.rcc.hsi = true;
-    config.rcc.mux = ClockSrc::PLL1_R;
+    config.rcc.sys = Sysclk::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 80Mhz clock (16 / 1 * 10 / 2)
         source: PllSource::HSI,
diff --git a/examples/stm32l5/src/bin/usb_hid_mouse.rs b/examples/stm32l5/src/bin/usb_hid_mouse.rs
index 7c8a8ebfb..c51ed96e0 100644
--- a/examples/stm32l5/src/bin/usb_hid_mouse.rs
+++ b/examples/stm32l5/src/bin/usb_hid_mouse.rs
@@ -22,7 +22,7 @@ bind_interrupts!(struct Irqs {
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     config.rcc.hsi = true;
-    config.rcc.mux = ClockSrc::PLL1_R;
+    config.rcc.sys = Sysclk::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 80Mhz clock (16 / 1 * 10 / 2)
         source: PllSource::HSI,
diff --git a/examples/stm32l5/src/bin/usb_serial.rs b/examples/stm32l5/src/bin/usb_serial.rs
index 75053ce4b..87987f2ce 100644
--- a/examples/stm32l5/src/bin/usb_serial.rs
+++ b/examples/stm32l5/src/bin/usb_serial.rs
@@ -20,7 +20,7 @@ bind_interrupts!(struct Irqs {
 async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     config.rcc.hsi = true;
-    config.rcc.mux = ClockSrc::PLL1_R;
+    config.rcc.sys = Sysclk::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 80Mhz clock (16 / 1 * 10 / 2)
         source: PllSource::HSI,
diff --git a/examples/stm32u5/src/bin/usb_serial.rs b/examples/stm32u5/src/bin/usb_serial.rs
index 99cdeacc9..61851e5a2 100644
--- a/examples/stm32u5/src/bin/usb_serial.rs
+++ b/examples/stm32u5/src/bin/usb_serial.rs
@@ -32,7 +32,7 @@ async fn main(_spawner: Spawner) {
             divq: None,
             divr: Some(PllDiv::DIV1), // 160 MHz
         });
-        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.sys = Sysclk::PLL1_R;
         config.rcc.voltage_range = VoltageScale::RANGE1;
         config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB
     }
diff --git a/examples/stm32wl/src/bin/random.rs b/examples/stm32wl/src/bin/random.rs
index 3610392be..8e9fe02b2 100644
--- a/examples/stm32wl/src/bin/random.rs
+++ b/examples/stm32wl/src/bin/random.rs
@@ -22,7 +22,7 @@ async fn main(_spawner: Spawner) {
             mode: HseMode::Bypass,
             prescaler: HsePrescaler::DIV1,
         });
-        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.sys = Sysclk::PLL1_R;
         config.rcc.pll = Some(Pll {
             source: PllSource::HSE,
             prediv: PllPreDiv::DIV2,
diff --git a/examples/stm32wl/src/bin/rtc.rs b/examples/stm32wl/src/bin/rtc.rs
index 4738d5770..0c26426ef 100644
--- a/examples/stm32wl/src/bin/rtc.rs
+++ b/examples/stm32wl/src/bin/rtc.rs
@@ -21,7 +21,7 @@ async fn main(_spawner: Spawner) {
             mode: HseMode::Bypass,
             prescaler: HsePrescaler::DIV1,
         });
-        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.sys = Sysclk::PLL1_R;
         config.rcc.pll = Some(Pll {
             source: PllSource::HSE,
             prediv: PllPreDiv::DIV2,
diff --git a/examples/stm32wl/src/bin/uart_async.rs b/examples/stm32wl/src/bin/uart_async.rs
index 8e545834c..3637243a0 100644
--- a/examples/stm32wl/src/bin/uart_async.rs
+++ b/examples/stm32wl/src/bin/uart_async.rs
@@ -20,7 +20,7 @@ but can be surely changed for your needs.
 #[embassy_executor::main]
 async fn main(_spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
-    config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE;
+    config.rcc.sys = embassy_stm32::rcc::Sysclk::HSE;
     let p = embassy_stm32::init(config);
 
     defmt::info!("Starting system");
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 1e6b1cce9..7b9585afd 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -527,7 +527,7 @@ pub fn config() -> Config {
     #[cfg(any(feature = "stm32l496zg", feature = "stm32l4a6zg", feature = "stm32l4r5zi"))]
     {
         use embassy_stm32::rcc::*;
-        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.sys = Sysclk::PLL1_R;
         config.rcc.hsi = true;
         config.rcc.pll = Some(Pll {
             source: PllSource::HSI,
@@ -547,7 +547,7 @@ pub fn config() -> Config {
             mode: HseMode::Bypass,
             prescaler: HsePrescaler::DIV1,
         });
-        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.sys = Sysclk::PLL1_R;
         config.rcc.pll = Some(Pll {
             source: PllSource::HSE,
             prediv: PllPreDiv::DIV2,
@@ -562,7 +562,7 @@ pub fn config() -> Config {
     {
         use embassy_stm32::rcc::*;
         config.rcc.hsi = true;
-        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.sys = Sysclk::PLL1_R;
         config.rcc.pll = Some(Pll {
             // 110Mhz clock (16 / 4 * 55 / 2)
             source: PllSource::HSI,
@@ -586,7 +586,7 @@ pub fn config() -> Config {
             divq: None,
             divr: Some(PllDiv::DIV1), // 160 MHz
         });
-        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.sys = Sysclk::PLL1_R;
         config.rcc.voltage_range = VoltageScale::RANGE1;
         config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB
     }
@@ -594,7 +594,7 @@ pub fn config() -> Config {
     #[cfg(feature = "stm32wba52cg")]
     {
         use embassy_stm32::rcc::*;
-        config.rcc.mux = ClockSrc::HSI;
+        config.rcc.sys = Sysclk::HSI;
 
         embassy_stm32::pac::RCC.ccipr2().write(|w| {
             w.set_rngsel(embassy_stm32::pac::rcc::vals::Rngsel::HSI);
@@ -610,7 +610,7 @@ pub fn config() -> Config {
             mul: PllMul::MUL4,
             div: PllDiv::DIV2, // 32Mhz clock (16 * 4 / 2)
         });
-        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.sys = Sysclk::PLL1_R;
     }
 
     #[cfg(any(feature = "stm32l152re"))]
@@ -622,7 +622,7 @@ pub fn config() -> Config {
             mul: PllMul::MUL4,
             div: PllDiv::DIV2, // 32Mhz clock (16 * 4 / 2)
         });
-        config.rcc.mux = ClockSrc::PLL1_R;
+        config.rcc.sys = Sysclk::PLL1_R;
     }
 
     config