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authorDario Nieuwenhuis <[email protected]>2024-03-23 01:44:46 +0100
committerDario Nieuwenhuis <[email protected]>2024-03-23 01:45:19 +0100
commit4aa4ea99c2c860d3c3012fee55db9b824d2ad2ef (patch)
tree604387d49c688c998bb548dd85b12baa2f839bdc
parentcb1e4e684e6767ba5bcaa018d60ab5c566b19490 (diff)
use private_bounds for sealed traits.
-rw-r--r--embassy-hal-internal/src/interrupt.rs8
-rw-r--r--embassy-net-wiznet/src/chip/mod.rs73
-rw-r--r--embassy-net-wiznet/src/chip/w5100s.rs2
-rw-r--r--embassy-net-wiznet/src/chip/w5500.rs2
-rw-r--r--embassy-usb/src/msos.rs28
5 files changed, 49 insertions, 64 deletions
diff --git a/embassy-hal-internal/src/interrupt.rs b/embassy-hal-internal/src/interrupt.rs
index 19dabcf6f..5e64dce9d 100644
--- a/embassy-hal-internal/src/interrupt.rs
+++ b/embassy-hal-internal/src/interrupt.rs
@@ -30,14 +30,12 @@ macro_rules! interrupt_mod {
30 pub mod typelevel { 30 pub mod typelevel {
31 use super::InterruptExt; 31 use super::InterruptExt;
32 32
33 mod sealed { 33 trait SealedInterrupt {}
34 pub trait Interrupt {}
35 }
36 34
37 /// Type-level interrupt. 35 /// Type-level interrupt.
38 /// 36 ///
39 /// This trait is implemented for all typelevel interrupt types in this module. 37 /// This trait is implemented for all typelevel interrupt types in this module.
40 pub trait Interrupt: sealed::Interrupt { 38 pub trait Interrupt: SealedInterrupt {
41 39
42 /// Interrupt enum variant. 40 /// Interrupt enum variant.
43 /// 41 ///
@@ -105,7 +103,7 @@ macro_rules! interrupt_mod {
105 #[doc=stringify!($irqs)] 103 #[doc=stringify!($irqs)]
106 #[doc=" typelevel interrupt."] 104 #[doc=" typelevel interrupt."]
107 pub enum $irqs {} 105 pub enum $irqs {}
108 impl sealed::Interrupt for $irqs{} 106 impl SealedInterrupt for $irqs{}
109 impl Interrupt for $irqs { 107 impl Interrupt for $irqs {
110 const IRQ: super::Interrupt = super::Interrupt::$irqs; 108 const IRQ: super::Interrupt = super::Interrupt::$irqs;
111 } 109 }
diff --git a/embassy-net-wiznet/src/chip/mod.rs b/embassy-net-wiznet/src/chip/mod.rs
index b987c2b36..e1f963d95 100644
--- a/embassy-net-wiznet/src/chip/mod.rs
+++ b/embassy-net-wiznet/src/chip/mod.rs
@@ -2,49 +2,40 @@
2mod w5500; 2mod w5500;
3pub use w5500::W5500; 3pub use w5500::W5500;
4mod w5100s; 4mod w5100s;
5use embedded_hal_async::spi::SpiDevice;
5pub use w5100s::W5100S; 6pub use w5100s::W5100S;
6 7
7pub(crate) mod sealed { 8pub(crate) trait SealedChip {
8 use embedded_hal_async::spi::SpiDevice; 9 type Address;
9 10
10 pub trait Chip { 11 const COMMON_MODE: Self::Address;
11 type Address; 12 const COMMON_MAC: Self::Address;
12 13 const COMMON_SOCKET_INTR: Self::Address;
13 const COMMON_MODE: Self::Address; 14 const COMMON_PHY_CFG: Self::Address;
14 const COMMON_MAC: Self::Address; 15 const SOCKET_MODE: Self::Address;
15 const COMMON_SOCKET_INTR: Self::Address; 16 const SOCKET_COMMAND: Self::Address;
16 const COMMON_PHY_CFG: Self::Address; 17 const SOCKET_RXBUF_SIZE: Self::Address;
17 const SOCKET_MODE: Self::Address; 18 const SOCKET_TXBUF_SIZE: Self::Address;
18 const SOCKET_COMMAND: Self::Address; 19 const SOCKET_TX_FREE_SIZE: Self::Address;
19 const SOCKET_RXBUF_SIZE: Self::Address; 20 const SOCKET_TX_DATA_WRITE_PTR: Self::Address;
20 const SOCKET_TXBUF_SIZE: Self::Address; 21 const SOCKET_RECVD_SIZE: Self::Address;
21 const SOCKET_TX_FREE_SIZE: Self::Address; 22 const SOCKET_RX_DATA_READ_PTR: Self::Address;
22 const SOCKET_TX_DATA_WRITE_PTR: Self::Address; 23 const SOCKET_INTR_MASK: Self::Address;
23 const SOCKET_RECVD_SIZE: Self::Address; 24 const SOCKET_INTR: Self::Address;
24 const SOCKET_RX_DATA_READ_PTR: Self::Address; 25
25 const SOCKET_INTR_MASK: Self::Address; 26 const SOCKET_MODE_VALUE: u8;
26 const SOCKET_INTR: Self::Address; 27
27 28 const BUF_SIZE: u16;
28 const SOCKET_MODE_VALUE: u8; 29 const AUTO_WRAP: bool;
29 30
30 const BUF_SIZE: u16; 31 fn rx_addr(addr: u16) -> Self::Address;
31 const AUTO_WRAP: bool; 32 fn tx_addr(addr: u16) -> Self::Address;
32 33
33 fn rx_addr(addr: u16) -> Self::Address; 34 async fn bus_read<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &mut [u8])
34 fn tx_addr(addr: u16) -> Self::Address; 35 -> Result<(), SPI::Error>;
35 36 async fn bus_write<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &[u8]) -> Result<(), SPI::Error>;
36 async fn bus_read<SPI: SpiDevice>(
37 spi: &mut SPI,
38 address: Self::Address,
39 data: &mut [u8],
40 ) -> Result<(), SPI::Error>;
41 async fn bus_write<SPI: SpiDevice>(
42 spi: &mut SPI,
43 address: Self::Address,
44 data: &[u8],
45 ) -> Result<(), SPI::Error>;
46 }
47} 37}
48 38
49/// Trait for Wiznet chips. 39/// Trait for Wiznet chips.
50pub trait Chip: sealed::Chip {} 40#[allow(private_bounds)]
41pub trait Chip: SealedChip {}
diff --git a/embassy-net-wiznet/src/chip/w5100s.rs b/embassy-net-wiznet/src/chip/w5100s.rs
index 7d328bce5..23ce3ed83 100644
--- a/embassy-net-wiznet/src/chip/w5100s.rs
+++ b/embassy-net-wiznet/src/chip/w5100s.rs
@@ -8,7 +8,7 @@ const RX_BASE: u16 = 0x6000;
8pub enum W5100S {} 8pub enum W5100S {}
9 9
10impl super::Chip for W5100S {} 10impl super::Chip for W5100S {}
11impl super::sealed::Chip for W5100S { 11impl super::SealedChip for W5100S {
12 type Address = u16; 12 type Address = u16;
13 13
14 const COMMON_MODE: Self::Address = 0x00; 14 const COMMON_MODE: Self::Address = 0x00;
diff --git a/embassy-net-wiznet/src/chip/w5500.rs b/embassy-net-wiznet/src/chip/w5500.rs
index 16236126d..12e610ea2 100644
--- a/embassy-net-wiznet/src/chip/w5500.rs
+++ b/embassy-net-wiznet/src/chip/w5500.rs
@@ -12,7 +12,7 @@ pub enum RegisterBlock {
12pub enum W5500 {} 12pub enum W5500 {}
13 13
14impl super::Chip for W5500 {} 14impl super::Chip for W5500 {}
15impl super::sealed::Chip for W5500 { 15impl super::SealedChip for W5500 {
16 type Address = (RegisterBlock, u16); 16 type Address = (RegisterBlock, u16);
17 17
18 const COMMON_MODE: Self::Address = (RegisterBlock::Common, 0x00); 18 const COMMON_MODE: Self::Address = (RegisterBlock::Common, 0x00);
diff --git a/embassy-usb/src/msos.rs b/embassy-usb/src/msos.rs
index a285a3ccd..25936d084 100644
--- a/embassy-usb/src/msos.rs
+++ b/embassy-usb/src/msos.rs
@@ -226,27 +226,21 @@ pub mod windows_version {
226 pub const WIN10: u32 = 0x0A000000; 226 pub const WIN10: u32 = 0x0A000000;
227} 227}
228 228
229mod sealed { 229/// A trait for descriptors
230 use core::mem::size_of; 230trait Descriptor: Sized {
231 const TYPE: DescriptorType;
231 232
232 /// A trait for descriptors 233 /// The size of the descriptor's header.
233 pub trait Descriptor: Sized { 234 fn size(&self) -> usize {
234 const TYPE: super::DescriptorType; 235 size_of::<Self>()
235
236 /// The size of the descriptor's header.
237 fn size(&self) -> usize {
238 size_of::<Self>()
239 }
240
241 fn write_to(&self, buf: &mut [u8]);
242 } 236 }
243 237
244 pub trait DescriptorSet: Descriptor { 238 fn write_to(&self, buf: &mut [u8]);
245 const LENGTH_OFFSET: usize;
246 }
247} 239}
248 240
249use sealed::*; 241trait DescriptorSet: Descriptor {
242 const LENGTH_OFFSET: usize;
243}
250 244
251/// Copies the data of `t` into `buf`. 245/// Copies the data of `t` into `buf`.
252/// 246///
@@ -412,9 +406,11 @@ impl DescriptorSet for FunctionSubsetHeader {
412// Feature Descriptors 406// Feature Descriptors
413 407
414/// A marker trait for feature descriptors that are valid at the device level. 408/// A marker trait for feature descriptors that are valid at the device level.
409#[allow(private_bounds)]
415pub trait DeviceLevelDescriptor: Descriptor {} 410pub trait DeviceLevelDescriptor: Descriptor {}
416 411
417/// A marker trait for feature descriptors that are valid at the function level. 412/// A marker trait for feature descriptors that are valid at the function level.
413#[allow(private_bounds)]
418pub trait FunctionLevelDescriptor: Descriptor {} 414pub trait FunctionLevelDescriptor: Descriptor {}
419 415
420/// Table 13. Microsoft OS 2.0 compatible ID descriptor. 416/// Table 13. Microsoft OS 2.0 compatible ID descriptor.